Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13101600	8769	0	0
alert_regwen_rd_A	13101600	5119	0	0
cpu_regwen_rd_A	13101600	5145	0	0
sw_rst_ctrl_n_0_rd_A	13101600	10160	0	0
sw_rst_ctrl_n_1_rd_A	13101600	10286	0	0
sw_rst_ctrl_n_2_rd_A	13101600	10131	0	0
sw_rst_ctrl_n_3_rd_A	13101600	10118	0	0
sw_rst_ctrl_n_4_rd_A	13101600	10062	0	0
sw_rst_ctrl_n_5_rd_A	13101600	10456	0	0
sw_rst_ctrl_n_6_rd_A	13101600	10347	0	0
sw_rst_ctrl_n_7_rd_A	13101600	10254	0	0
sw_rst_regwen_0_rd_A	13101600	5803	0	0
sw_rst_regwen_1_rd_A	13101600	5742	0	0
sw_rst_regwen_2_rd_A	13101600	5929	0	0
sw_rst_regwen_3_rd_A	13101600	5899	0	0
sw_rst_regwen_4_rd_A	13101600	5658	0	0
sw_rst_regwen_5_rd_A	13101600	5727	0	0
sw_rst_regwen_6_rd_A	13101600	5656	0	0
sw_rst_regwen_7_rd_A	13101600	5838	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	8769	0	0
T66	11911	1	0	0
T67	20942	3	0	0
T72	6163	398	0	0
T73	4242	11	0	0
T74	3411	557	0	0
T75	4635	17	0	0
T76	20358	3	0	0
T100	2790	353	0	0
T101	2919	180	0	0
T102	4170	164	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5119	0	0
T69	189846	0	0	0
T115	0	27	0	0
T116	0	29	0	0
T119	35655	40	0	0
T120	12838	0	0	0
T144	0	125	0	0
T145	0	32	0	0
T146	0	331	0	0
T147	0	94	0	0
T148	0	64	0	0
T149	0	374	0	0
T150	0	86	0	0
T151	1921	0	0	0
T152	2037	0	0	0
T153	1918	0	0	0
T154	6774	0	0	0
T155	2427	0	0	0
T156	5275	0	0	0
T157	14076	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5145	0	0
T69	189846	0	0	0
T115	0	61	0	0
T116	0	22	0	0
T119	35655	21	0	0
T120	12838	0	0	0
T144	0	146	0	0
T145	0	18	0	0
T146	0	334	0	0
T147	0	80	0	0
T148	0	63	0	0
T149	0	433	0	0
T150	0	96	0	0
T151	1921	0	0	0
T152	2037	0	0	0
T153	1918	0	0	0
T154	6774	0	0	0
T155	2427	0	0	0
T156	5275	0	0	0
T157	14076	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10160	0	0
T7	8871	150	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	20	0	0
T25	1641	0	0	0
T36	0	117	0	0
T43	0	59	0	0
T57	0	137	0	0
T62	12019	194	0	0
T63	0	139	0	0
T95	0	15	0	0
T158	0	2	0	0
T159	0	6	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10286	0	0
T7	8871	129	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	125	0	0
T43	0	45	0	0
T57	0	102	0	0
T62	12019	196	0	0
T63	0	163	0	0
T95	0	10	0	0
T158	0	7	0	0
T159	0	21	0	0
T160	0	8	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10131	0	0
T7	8871	130	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	15	0	0
T25	1641	0	0	0
T36	0	117	0	0
T43	0	65	0	0
T57	0	119	0	0
T62	12019	194	0	0
T63	0	140	0	0
T95	0	7	0	0
T158	0	9	0	0
T159	0	27	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10118	0	0
T7	8871	127	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	15	0	0
T25	1641	0	0	0
T36	0	126	0	0
T43	0	63	0	0
T57	0	129	0	0
T62	12019	196	0	0
T63	0	162	0	0
T95	0	18	0	0
T158	0	6	0	0
T159	0	26	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10062	0	0
T7	8871	122	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	14	0	0
T25	1641	0	0	0
T36	0	132	0	0
T43	0	63	0	0
T57	0	112	0	0
T62	12019	195	0	0
T63	0	148	0	0
T95	0	9	0	0
T158	0	3	0	0
T159	0	25	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10456	0	0
T7	8871	122	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	10	0	0
T25	1641	0	0	0
T36	0	164	0	0
T43	0	57	0	0
T57	0	107	0	0
T62	12019	207	0	0
T63	0	154	0	0
T95	0	7	0	0
T159	0	30	0	0
T160	0	2	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10347	0	0
T7	8871	138	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	9	0	0
T25	1641	0	0	0
T36	0	111	0	0
T43	0	69	0	0
T57	0	153	0	0
T62	12019	243	0	0
T63	0	154	0	0
T95	0	14	0	0
T158	0	3	0	0
T159	0	28	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	10254	0	0
T7	8871	124	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T24	0	19	0	0
T25	1641	0	0	0
T36	0	165	0	0
T43	0	56	0	0
T57	0	115	0	0
T62	12019	211	0	0
T63	0	142	0	0
T95	0	8	0	0
T158	0	1	0	0
T159	0	33	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5803	0	0
T7	8871	20	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	19	0	0
T57	0	36	0	0
T62	12019	45	0	0
T63	0	31	0	0
T95	0	6	0	0
T119	0	25	0	0
T160	0	6	0	0
T161	0	31	0	0
T162	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5742	0	0
T7	8871	36	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	38	0	0
T57	0	31	0	0
T62	12019	41	0	0
T63	0	39	0	0
T95	0	5	0	0
T119	0	14	0	0
T160	0	4	0	0
T161	0	32	0	0
T162	0	9	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5929	0	0
T7	8871	50	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	50	0	0
T57	0	36	0	0
T62	12019	31	0	0
T63	0	51	0	0
T95	0	7	0	0
T119	0	33	0	0
T160	0	1	0	0
T161	0	22	0	0
T162	0	16	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5899	0	0
T7	8871	33	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	17	0	0
T57	0	30	0	0
T62	12019	30	0	0
T63	0	21	0	0
T95	0	4	0	0
T119	0	24	0	0
T160	0	3	0	0
T161	0	24	0	0
T162	0	11	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5658	0	0
T7	8871	25	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	47	0	0
T57	0	42	0	0
T62	12019	24	0	0
T63	0	40	0	0
T95	0	8	0	0
T119	0	37	0	0
T161	0	52	0	0
T162	0	6	0	0
T163	0	16	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5727	0	0
T7	8871	39	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	29	0	0
T57	0	24	0	0
T62	12019	46	0	0
T63	0	30	0	0
T95	0	6	0	0
T119	0	16	0	0
T160	0	3	0	0
T161	0	41	0	0
T162	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5656	0	0
T7	8871	34	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	31	0	0
T57	0	43	0	0
T62	12019	41	0	0
T63	0	33	0	0
T95	0	4	0	0
T119	0	32	0	0
T160	0	8	0	0
T161	0	44	0	0
T162	0	13	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13101600	5838	0	0
T7	8871	21	0	0
T8	4638	0	0	0
T9	2052	0	0	0
T10	4364	0	0	0
T11	1962	0	0	0
T12	3535	0	0	0
T13	4266	0	0	0
T14	6420	0	0	0
T25	1641	0	0	0
T36	0	18	0	0
T57	0	33	0	0
T62	12019	34	0	0
T63	0	25	0	0
T95	0	8	0	0
T119	0	22	0	0
T160	0	11	0	0
T161	0	41	0	0
T162	0	11	0	0