Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total test records in report: 606
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html

T292 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.931816833 Sep 24 09:38:17 PM UTC 24 Sep 24 09:38:23 PM UTC 24 1220953881 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3727184404 Sep 24 09:38:17 PM UTC 24 Sep 24 09:38:23 PM UTC 24 1101163337 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.3067257206 Sep 24 09:38:07 PM UTC 24 Sep 24 09:38:23 PM UTC 24 3355018600 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.720892428 Sep 24 09:38:16 PM UTC 24 Sep 24 09:38:24 PM UTC 24 1270289246 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3143089738 Sep 24 09:38:15 PM UTC 24 Sep 24 09:38:24 PM UTC 24 1994001794 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2160350900 Sep 24 09:38:19 PM UTC 24 Sep 24 09:38:26 PM UTC 24 929797736 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.314678740 Sep 24 09:37:59 PM UTC 24 Sep 24 09:38:26 PM UTC 24 5098811683 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.542345063 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:26 PM UTC 24 5517402389 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.2482295883 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:27 PM UTC 24 99244287 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.1034355664 Sep 24 09:38:18 PM UTC 24 Sep 24 09:38:27 PM UTC 24 2248334347 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.812590339 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:29 PM UTC 24 762503357 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2473043756 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:31 PM UTC 24 1264966016 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1208151196 Sep 24 09:38:29 PM UTC 24 Sep 24 09:38:32 PM UTC 24 144736283 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3401742627 Sep 24 09:38:27 PM UTC 24 Sep 24 09:38:32 PM UTC 24 79916406 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.4185514223 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 68359634 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1864760820 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 129775364 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1025055012 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 193665822 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.350743829 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 130438515 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2813316745 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 301491566 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.2053644282 Sep 24 09:38:21 PM UTC 24 Sep 24 09:38:33 PM UTC 24 144245155 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3630289298 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:33 PM UTC 24 183623883 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3261527441 Sep 24 09:38:23 PM UTC 24 Sep 24 09:38:33 PM UTC 24 254784407 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.513477905 Sep 24 09:37:55 PM UTC 24 Sep 24 09:38:34 PM UTC 24 9485481447 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1666712930 Sep 24 09:38:27 PM UTC 24 Sep 24 09:38:34 PM UTC 24 347691658 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.4073099178 Sep 24 09:38:18 PM UTC 24 Sep 24 09:38:35 PM UTC 24 4347651613 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.2727355989 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:36 PM UTC 24 817327568 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3592834176 Sep 24 09:37:57 PM UTC 24 Sep 24 09:38:36 PM UTC 24 8918276140 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.425331975 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:36 PM UTC 24 133116724 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.2861659571 Sep 24 09:38:27 PM UTC 24 Sep 24 09:38:37 PM UTC 24 1085585184 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2656261125 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:37 PM UTC 24 174653848 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3590321095 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:37 PM UTC 24 185315264 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4060438883 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:37 PM UTC 24 149480363 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.687369526 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:37 PM UTC 24 101149258 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.727806781 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:37 PM UTC 24 117855615 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.602676167 Sep 24 09:38:25 PM UTC 24 Sep 24 09:38:37 PM UTC 24 77821502 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1608703697 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:37 PM UTC 24 302870106 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3018091018 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:37 PM UTC 24 150666032 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.2529262102 Sep 24 09:38:24 PM UTC 24 Sep 24 09:38:37 PM UTC 24 129071747 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.664982525 Sep 24 09:38:32 PM UTC 24 Sep 24 09:38:37 PM UTC 24 301787660 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.1355616254 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:37 PM UTC 24 73439983 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1385759493 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:37 PM UTC 24 301824903 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1759917391 Sep 24 09:38:25 PM UTC 24 Sep 24 09:38:37 PM UTC 24 301245712 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.2594609794 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:38 PM UTC 24 150746212 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.373221235 Sep 24 09:38:25 PM UTC 24 Sep 24 09:38:38 PM UTC 24 248158426 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.4034183723 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:38 PM UTC 24 307910080 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.706207055 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:38 PM UTC 24 131485283 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.1171887058 Sep 24 09:38:30 PM UTC 24 Sep 24 09:38:38 PM UTC 24 2275169340 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.1757462003 Sep 24 09:37:42 PM UTC 24 Sep 24 09:38:38 PM UTC 24 15805871243 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2404931696 Sep 24 09:38:11 PM UTC 24 Sep 24 09:38:39 PM UTC 24 7874345717 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.139694169 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:39 PM UTC 24 1922376731 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.1051638140 Sep 24 09:38:15 PM UTC 24 Sep 24 09:38:40 PM UTC 24 5521032395 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.1712778135 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:40 PM UTC 24 965423110 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.2195797476 Sep 24 09:37:52 PM UTC 24 Sep 24 09:38:40 PM UTC 24 13663843373 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.938597734 Sep 24 09:38:20 PM UTC 24 Sep 24 09:38:41 PM UTC 24 2446255700 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.1477117483 Sep 24 09:38:26 PM UTC 24 Sep 24 09:38:41 PM UTC 24 87455782 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1089934600 Sep 24 09:38:33 PM UTC 24 Sep 24 09:38:41 PM UTC 24 72983171 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1095214273 Sep 24 09:38:36 PM UTC 24 Sep 24 09:38:41 PM UTC 24 85243767 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.945355468 Sep 24 09:38:36 PM UTC 24 Sep 24 09:38:41 PM UTC 24 166406928 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3480023201 Sep 24 09:38:36 PM UTC 24 Sep 24 09:38:42 PM UTC 24 187375056 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.894148452 Sep 24 09:38:35 PM UTC 24 Sep 24 09:38:43 PM UTC 24 1975089949 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.3591155320 Sep 24 09:38:22 PM UTC 24 Sep 24 09:38:44 PM UTC 24 2441434984 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.2863600008 Sep 24 09:38:33 PM UTC 24 Sep 24 09:38:46 PM UTC 24 1251413019 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.2903151436 Sep 24 09:38:38 PM UTC 24 Sep 24 09:38:46 PM UTC 24 142360479 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.2484775458 Sep 24 09:38:41 PM UTC 24 Sep 24 09:38:46 PM UTC 24 188701876 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1186602841 Sep 24 09:38:38 PM UTC 24 Sep 24 09:38:47 PM UTC 24 137360909 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.529811096 Sep 24 09:38:44 PM UTC 24 Sep 24 09:38:47 PM UTC 24 163165749 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4101134948 Sep 24 09:38:44 PM UTC 24 Sep 24 09:38:47 PM UTC 24 156813827 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.769109194 Sep 24 09:38:44 PM UTC 24 Sep 24 09:38:48 PM UTC 24 467077124 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.912060328 Sep 24 09:38:09 PM UTC 24 Sep 24 09:38:50 PM UTC 24 9857577311 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.1488443209 Sep 24 09:38:44 PM UTC 24 Sep 24 09:38:51 PM UTC 24 1266159211 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.78474760 Sep 24 09:38:49 PM UTC 24 Sep 24 09:38:52 PM UTC 24 107079746 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.4056354329 Sep 24 09:38:13 PM UTC 24 Sep 24 09:38:52 PM UTC 24 11918467488 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1368581466 Sep 24 09:38:38 PM UTC 24 Sep 24 09:38:53 PM UTC 24 2083635899 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.1419954724 Sep 24 09:38:01 PM UTC 24 Sep 24 09:38:53 PM UTC 24 16131406563 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.1143427210 Sep 24 09:38:48 PM UTC 24 Sep 24 09:38:57 PM UTC 24 78447049 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.1849478676 Sep 24 09:38:48 PM UTC 24 Sep 24 09:38:57 PM UTC 24 124694942 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2619170324 Sep 24 09:38:48 PM UTC 24 Sep 24 09:38:57 PM UTC 24 231789446 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.3049172387 Sep 24 09:38:48 PM UTC 24 Sep 24 09:38:58 PM UTC 24 267160684 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1171475651 Sep 24 09:38:54 PM UTC 24 Sep 24 09:39:00 PM UTC 24 703206651 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.132578962 Sep 24 09:38:50 PM UTC 24 Sep 24 09:39:00 PM UTC 24 2457169056 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.3248020462 Sep 24 09:38:53 PM UTC 24 Sep 24 09:39:02 PM UTC 24 82035144 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3937937329 Sep 24 09:38:53 PM UTC 24 Sep 24 09:39:02 PM UTC 24 196488927 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1347146363 Sep 24 09:39:00 PM UTC 24 Sep 24 09:39:02 PM UTC 24 301113232 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.3998939392 Sep 24 09:38:43 PM UTC 24 Sep 24 09:39:02 PM UTC 24 71908377 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1569821376 Sep 24 09:38:43 PM UTC 24 Sep 24 09:39:03 PM UTC 24 139946084 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3275046230 Sep 24 09:38:43 PM UTC 24 Sep 24 09:39:03 PM UTC 24 302039665 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.3457132510 Sep 24 09:38:43 PM UTC 24 Sep 24 09:39:03 PM UTC 24 254485006 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1698691194 Sep 24 09:38:45 PM UTC 24 Sep 24 09:39:03 PM UTC 24 2424505825 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3054311138 Sep 24 09:38:58 PM UTC 24 Sep 24 09:39:03 PM UTC 24 168819768 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1520127349 Sep 24 09:38:58 PM UTC 24 Sep 24 09:39:04 PM UTC 24 348609429 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.3108454192 Sep 24 09:38:38 PM UTC 24 Sep 24 09:39:05 PM UTC 24 2269303162 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.425403539 Sep 24 09:38:35 PM UTC 24 Sep 24 09:39:05 PM UTC 24 8917153383 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.1094100188 Sep 24 09:38:48 PM UTC 24 Sep 24 09:39:05 PM UTC 24 788502991 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2681264176 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:06 PM UTC 24 170952959 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.2196737496 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:06 PM UTC 24 122273947 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.3797682451 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:07 PM UTC 24 108608029 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.1851161282 Sep 24 09:38:44 PM UTC 24 Sep 24 09:39:07 PM UTC 24 1377162729 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.2153357778 Sep 24 09:38:59 PM UTC 24 Sep 24 09:39:08 PM UTC 24 1958049606 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.3964044707 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 156291440 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1408262621 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 118617697 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.2828397189 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 132648704 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1813285081 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 77905571 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2141686691 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 301866453 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2779549437 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 177567290 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.2020399319 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:12 PM UTC 24 137458005 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.251092648 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:13 PM UTC 24 143861215 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.1982338108 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:13 PM UTC 24 227731282 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.81281727 Sep 24 09:38:58 PM UTC 24 Sep 24 09:39:13 PM UTC 24 119370314 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1595892105 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:13 PM UTC 24 110406552 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.313785259 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:14 PM UTC 24 64574341 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3466773256 Sep 24 09:38:51 PM UTC 24 Sep 24 09:39:14 PM UTC 24 301409986 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.3219210715 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:14 PM UTC 24 186703853 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.846861460 Sep 24 09:38:54 PM UTC 24 Sep 24 09:39:14 PM UTC 24 119942540 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1757875120 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:14 PM UTC 24 158567395 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2440295467 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:14 PM UTC 24 192458073 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2329933011 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:15 PM UTC 24 132285056 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.830876484 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:16 PM UTC 24 733533695 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2915574101 Sep 24 09:39:14 PM UTC 24 Sep 24 09:39:17 PM UTC 24 148945817 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.636975578 Sep 24 09:39:14 PM UTC 24 Sep 24 09:39:17 PM UTC 24 302745096 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.732152446 Sep 24 09:38:41 PM UTC 24 Sep 24 09:39:17 PM UTC 24 1277287545 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.939369335 Sep 24 09:39:06 PM UTC 24 Sep 24 09:39:17 PM UTC 24 80916036 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1231317735 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:18 PM UTC 24 1972424857 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2534441324 Sep 24 09:39:06 PM UTC 24 Sep 24 09:39:18 PM UTC 24 99282481 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.2143697970 Sep 24 09:38:46 PM UTC 24 Sep 24 09:39:18 PM UTC 24 77322223 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3803458949 Sep 24 09:39:06 PM UTC 24 Sep 24 09:39:18 PM UTC 24 302323551 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.1207118759 Sep 24 09:39:13 PM UTC 24 Sep 24 09:39:18 PM UTC 24 142325972 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.4133180078 Sep 24 09:39:14 PM UTC 24 Sep 24 09:39:19 PM UTC 24 113485312 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.308727624 Sep 24 09:39:09 PM UTC 24 Sep 24 09:39:19 PM UTC 24 2250431705 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.4146064764 Sep 24 09:39:04 PM UTC 24 Sep 24 09:39:19 PM UTC 24 1972705003 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.3452675869 Sep 24 09:39:14 PM UTC 24 Sep 24 09:39:20 PM UTC 24 354366584 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2517456053 Sep 24 09:38:25 PM UTC 24 Sep 24 09:39:21 PM UTC 24 12551957279 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.641344190 Sep 24 09:39:13 PM UTC 24 Sep 24 09:39:22 PM UTC 24 976823892 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.513812000 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 63703395 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.2623255535 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 155778247 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.1184902462 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 117355628 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.1075325507 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 67247350 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1626852104 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 168822641 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1339395681 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 301984404 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3913741570 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 146526978 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2077076649 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 208608229 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.1082216499 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:23 PM UTC 24 148787678 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.504623581 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:24 PM UTC 24 203567893 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.4147783721 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:24 PM UTC 24 142986218 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.866862399 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:24 PM UTC 24 66531116 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.747321518 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:24 PM UTC 24 103995606 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3464673871 Sep 24 09:39:06 PM UTC 24 Sep 24 09:39:24 PM UTC 24 1618715654 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2571647243 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:24 PM UTC 24 302869269 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.1602875133 Sep 24 09:38:51 PM UTC 24 Sep 24 09:39:24 PM UTC 24 3623180382 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1069905231 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:25 PM UTC 24 375909025 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1314038994 Sep 24 09:39:14 PM UTC 24 Sep 24 09:39:25 PM UTC 24 2465767664 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3309536337 Sep 24 09:39:06 PM UTC 24 Sep 24 09:39:26 PM UTC 24 2434221401 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1916834153 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:27 PM UTC 24 91731116 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.738785239 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:28 PM UTC 24 91444286 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.3976566747 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:28 PM UTC 24 70040346 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.4206400745 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:28 PM UTC 24 111075129 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2238915312 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:28 PM UTC 24 96737412 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.1065270724 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:28 PM UTC 24 205791930 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.1242267017 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:28 PM UTC 24 1532255541 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.4294597592 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:28 PM UTC 24 114621641 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1677646831 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:28 PM UTC 24 301870201 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2014218158 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:29 PM UTC 24 375745021 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.1602778215 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:29 PM UTC 24 64078329 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.1001189019 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:29 PM UTC 24 1902014237 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.489144044 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:29 PM UTC 24 82574979 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.1509905372 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:29 PM UTC 24 126028596 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.2212327192 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 210858405 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.2168927016 Sep 24 09:39:28 PM UTC 24 Sep 24 09:39:30 PM UTC 24 87396958 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.4253475827 Sep 24 09:38:43 PM UTC 24 Sep 24 09:39:30 PM UTC 24 8927314973 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.849761051 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 255662103 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4084401039 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 169192691 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1280229642 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 103115862 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1842406920 Sep 24 09:39:28 PM UTC 24 Sep 24 09:39:30 PM UTC 24 302331817 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.247045167 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 233484081 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1678489334 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 301122575 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.3398706856 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 364164129 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.1079657875 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:30 PM UTC 24 2255051104 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1078001012 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:30 PM UTC 24 126705783 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.4159152292 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:31 PM UTC 24 878907868 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.1459829043 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:32 PM UTC 24 796414411 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.4188360681 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:32 PM UTC 24 1271831563 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.1041648882 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:33 PM UTC 24 2457674624 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.868103875 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:33 PM UTC 24 1492004642 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.4227736935 Sep 24 09:39:27 PM UTC 24 Sep 24 09:39:34 PM UTC 24 1276953762 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1843931628 Sep 24 09:39:23 PM UTC 24 Sep 24 09:39:34 PM UTC 24 1761544828 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.3429924256 Sep 24 09:39:34 PM UTC 24 Sep 24 09:40:20 PM UTC 24 11321159710 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.512057853 Sep 24 09:39:28 PM UTC 24 Sep 24 09:39:36 PM UTC 24 1528377562 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3220728715 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:36 PM UTC 24 85040624 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.3626952837 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:36 PM UTC 24 69939771 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.1977558737 Sep 24 09:39:28 PM UTC 24 Sep 24 09:39:36 PM UTC 24 2242959664 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1463673789 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:36 PM UTC 24 62022552 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4035671633 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:36 PM UTC 24 172029085 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.709336627 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:36 PM UTC 24 231362182 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1745280491 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 303334780 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.3416063867 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 113111715 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2009382323 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 211873139 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.68783740 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 101195905 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.231603947 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 141067419 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3466665293 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 70372596 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.1398835842 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 112999767 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.169204800 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:37 PM UTC 24 300904095 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.2800404280 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:38 PM UTC 24 134367495 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.912198872 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:38 PM UTC 24 135532717 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3249689435 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:38 PM UTC 24 146154257 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.83127533 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:38 PM UTC 24 406200336 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.4110471801 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:38 PM UTC 24 194156705 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1491423280 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:38 PM UTC 24 302195095 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.61242079 Sep 24 09:39:22 PM UTC 24 Sep 24 09:39:38 PM UTC 24 4415311431 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.1048701335 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:39 PM UTC 24 396871675 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.409938533 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:41 PM UTC 24 1282370904 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3642507039 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:41 PM UTC 24 5438786638 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3386734423 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:42 PM UTC 24 1668460901 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.186084752 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:42 PM UTC 24 1269421840 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2492396867 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:43 PM UTC 24 2003551792 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.1769786063 Sep 24 09:39:35 PM UTC 24 Sep 24 09:39:44 PM UTC 24 1914511416 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.1572170006 Sep 24 09:39:02 PM UTC 24 Sep 24 09:39:44 PM UTC 24 8706009847 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.3921291372 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:44 PM UTC 24 57860438 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.2611159621 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:44 PM UTC 24 141198629 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.768851578 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:44 PM UTC 24 108484907 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.1953360716 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 133039031 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3957504800 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 170664843 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1578686808 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 302742162 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2748429042 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 67813287 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.1194092297 Sep 24 09:39:34 PM UTC 24 Sep 24 09:39:45 PM UTC 24 2431847567 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.4001063186 Sep 24 09:39:18 PM UTC 24 Sep 24 09:39:45 PM UTC 24 7018124536 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.492012766 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 192365399 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2845196816 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 67565085 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.773907527 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:45 PM UTC 24 301857841 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.701730973 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:46 PM UTC 24 134240503 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.2618420776 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:46 PM UTC 24 348494165 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3219025199 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:46 PM UTC 24 143446936 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.4247397391 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:46 PM UTC 24 226495111 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.283360858 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:46 PM UTC 24 291033398 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.2782594247 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:49 PM UTC 24 1309285284 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.614890095 Sep 24 09:38:38 PM UTC 24 Sep 24 09:39:49 PM UTC 24 9515028631 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.1745092706 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:50 PM UTC 24 1232908087 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3928558992 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:50 PM UTC 24 1270532681 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.2746970780 Sep 24 09:39:42 PM UTC 24 Sep 24 09:39:51 PM UTC 24 1951625642 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.1523651490 Sep 24 09:39:42 PM UTC 24 Sep 24 09:40:04 PM UTC 24 4328813669 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1375376762 Sep 24 09:39:42 PM UTC 24 Sep 24 09:40:05 PM UTC 24 4134186121 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.4114048205 Sep 24 09:39:34 PM UTC 24 Sep 24 09:40:06 PM UTC 24 6166835306 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.4118814108 Sep 24 09:39:42 PM UTC 24 Sep 24 09:40:15 PM UTC 24 8159963658 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.542736718 Sep 24 09:37:07 PM UTC 24 Sep 24 09:37:09 PM UTC 24 121368880 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.1588406292 Sep 24 09:37:08 PM UTC 24 Sep 24 09:37:10 PM UTC 24 77873150 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.882186442 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:25 PM UTC 24 507325566 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.228646233 Sep 24 09:37:06 PM UTC 24 Sep 24 09:37:11 PM UTC 24 259820426 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2271572967 Sep 24 09:37:06 PM UTC 24 Sep 24 09:37:11 PM UTC 24 914630139 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2672484005 Sep 24 09:37:09 PM UTC 24 Sep 24 09:37:12 PM UTC 24 80159181 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3833316517 Sep 24 09:37:08 PM UTC 24 Sep 24 09:37:12 PM UTC 24 350663740 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4105325942 Sep 24 09:37:09 PM UTC 24 Sep 24 09:37:12 PM UTC 24 188787718 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1222170688 Sep 24 09:37:09 PM UTC 24 Sep 24 09:37:12 PM UTC 24 143157830 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%