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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total test records in report: 606
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T532 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4268261729 Sep 24 09:37:10 PM UTC 24 Sep 24 09:37:13 PM UTC 24 150277832 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2958860751 Sep 24 09:37:11 PM UTC 24 Sep 24 09:37:13 PM UTC 24 81952576 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3952660021 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:15 PM UTC 24 104901063 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.418823476 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:15 PM UTC 24 77034250 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3438317342 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:15 PM UTC 24 205164265 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3671810817 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:15 PM UTC 24 146165005 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2954328200 Sep 24 09:37:10 PM UTC 24 Sep 24 09:37:15 PM UTC 24 869289748 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3126071113 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:15 PM UTC 24 119289144 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2259869550 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:16 PM UTC 24 121480702 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.961818761 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:16 PM UTC 24 66567930 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2764074624 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:16 PM UTC 24 477617837 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3534767094 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:16 PM UTC 24 210999524 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3478155148 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:17 PM UTC 24 125657048 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3983938696 Sep 24 09:37:08 PM UTC 24 Sep 24 09:37:17 PM UTC 24 483287752 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2024142127 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:17 PM UTC 24 175790940 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4109005074 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:17 PM UTC 24 913957337 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3289273419 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:17 PM UTC 24 360527079 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1502560444 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:19 PM UTC 24 772375522 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2891123051 Sep 24 09:37:14 PM UTC 24 Sep 24 09:37:19 PM UTC 24 271248643 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2805257370 Sep 24 09:37:17 PM UTC 24 Sep 24 09:37:19 PM UTC 24 75829724 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4176125604 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:19 PM UTC 24 93030271 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1358415926 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:19 PM UTC 24 814879615 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1732708911 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:19 PM UTC 24 68818882 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3911188261 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:19 PM UTC 24 234278853 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2396631149 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:19 PM UTC 24 180497851 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1779668011 Sep 24 09:37:17 PM UTC 24 Sep 24 09:37:19 PM UTC 24 111458241 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1689027597 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:24 PM UTC 24 281286229 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1120352936 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:20 PM UTC 24 436700153 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.223017373 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:20 PM UTC 24 348277568 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.697470709 Sep 24 09:37:12 PM UTC 24 Sep 24 09:37:20 PM UTC 24 489950382 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2445054902 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:20 PM UTC 24 77074163 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3395909737 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:20 PM UTC 24 114985138 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3128120643 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:20 PM UTC 24 71290673 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1687627832 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:20 PM UTC 24 61370780 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2224069411 Sep 24 09:37:16 PM UTC 24 Sep 24 09:37:20 PM UTC 24 213905399 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1855247257 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:21 PM UTC 24 282536983 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3876018836 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:21 PM UTC 24 216024737 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.41986166 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 93492450 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1126172609 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:21 PM UTC 24 136916315 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2303809436 Sep 24 09:37:17 PM UTC 24 Sep 24 09:37:21 PM UTC 24 275988945 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2647674650 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:21 PM UTC 24 490574036 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1336500326 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:22 PM UTC 24 61361110 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3607369966 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:22 PM UTC 24 65285854 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2489274688 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:22 PM UTC 24 182374902 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3186469512 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:22 PM UTC 24 211708700 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1140964862 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:22 PM UTC 24 240440572 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3867240097 Sep 24 09:37:19 PM UTC 24 Sep 24 09:37:23 PM UTC 24 277113387 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1023938615 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:23 PM UTC 24 951448084 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2078305077 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:23 PM UTC 24 68861160 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2001975252 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:23 PM UTC 24 83244077 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3410394827 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:23 PM UTC 24 67732206 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1027055306 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:23 PM UTC 24 119998044 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3429448161 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:24 PM UTC 24 115896829 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1348604092 Sep 24 09:37:18 PM UTC 24 Sep 24 09:37:24 PM UTC 24 659068293 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3735200605 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:24 PM UTC 24 866329670 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.24404686 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:24 PM UTC 24 95022887 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1306504975 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:24 PM UTC 24 178693334 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2198838668 Sep 24 09:37:19 PM UTC 24 Sep 24 09:37:24 PM UTC 24 891993932 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3276537028 Sep 24 09:37:20 PM UTC 24 Sep 24 09:37:24 PM UTC 24 201825415 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3914143244 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 136858274 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1194469542 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 73150641 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.830272991 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 109317693 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1941118640 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 141619635 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2528135412 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:25 PM UTC 24 96323703 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4040743988 Sep 24 09:37:22 PM UTC 24 Sep 24 09:37:25 PM UTC 24 260946927 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1370736169 Sep 24 09:37:21 PM UTC 24 Sep 24 09:37:26 PM UTC 24 798360773 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1308673027 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:26 PM UTC 24 71118136 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3941044262 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:26 PM UTC 24 118950863 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.409415741 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:27 PM UTC 24 114578745 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3701325733 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:27 PM UTC 24 76367463 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2982940323 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:27 PM UTC 24 230528896 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.543868521 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:27 PM UTC 24 420205351 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4217522839 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:27 PM UTC 24 883046074 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.579249023 Sep 24 09:37:23 PM UTC 24 Sep 24 09:37:27 PM UTC 24 913743158 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.594828088 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:27 PM UTC 24 286034895 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.762082517 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:27 PM UTC 24 426319340 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1840469959 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 93241948 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3267467380 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 84278273 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2466156894 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 67315545 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2762272045 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 71732937 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1630811386 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 103024587 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3250108777 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:28 PM UTC 24 60817155 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3592505836 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:28 PM UTC 24 384654849 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1762753939 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:29 PM UTC 24 123067080 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3550770264 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:29 PM UTC 24 137571308 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2287563842 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:29 PM UTC 24 438916919 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2653967748 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:29 PM UTC 24 202113610 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.491449936 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:29 PM UTC 24 282781806 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1858416466 Sep 24 09:37:24 PM UTC 24 Sep 24 09:37:29 PM UTC 24 952291843 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3940174861 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:29 PM UTC 24 221334085 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1436315623 Sep 24 09:37:27 PM UTC 24 Sep 24 09:37:30 PM UTC 24 118023296 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1826051967 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:30 PM UTC 24 68915830 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.829967023 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:30 PM UTC 24 142321773 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.819609663 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:30 PM UTC 24 61939920 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.366306301 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:30 PM UTC 24 127577194 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4031918831 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:30 PM UTC 24 142856781 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.33042268 Sep 24 09:37:27 PM UTC 24 Sep 24 09:37:30 PM UTC 24 279989860 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.694859378 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:31 PM UTC 24 446608495 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2609208453 Sep 24 09:37:27 PM UTC 24 Sep 24 09:37:31 PM UTC 24 201566967 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3629799842 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:31 PM UTC 24 466907128 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2827071693 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:31 PM UTC 24 790746000 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1473153148 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:31 PM UTC 24 499407032 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.4013368494 Sep 24 09:37:28 PM UTC 24 Sep 24 09:37:31 PM UTC 24 269360064 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4132285970 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 214452531 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3807545391 Sep 24 09:37:27 PM UTC 24 Sep 24 09:37:32 PM UTC 24 923623645 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1050717490 Sep 24 09:37:26 PM UTC 24 Sep 24 09:37:32 PM UTC 24 1341574546 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.503677718
Short name T5
Test name
Test status
Simulation time 202955838 ps
CPU time 1.5 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503677718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.503677718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2196949006
Short name T63
Test name
Test status
Simulation time 411742155 ps
CPU time 2.48 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196949006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2196949006
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1419868491
Short name T26
Test name
Test status
Simulation time 1271421893 ps
CPU time 5.94 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:37 PM UTC 24
Peak memory 244168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419868491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1419868491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4105325942
Short name T73
Test name
Test status
Simulation time 188787718 ps
CPU time 1.67 seconds
Started Sep 24 09:37:09 PM UTC 24
Finished Sep 24 09:37:12 PM UTC 24
Peak memory 217560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4105325942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w
ith_rand_reset.4105325942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.621734347
Short name T71
Test name
Test status
Simulation time 17366340459 ps
CPU time 29.6 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 243644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621734347 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.621734347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.2921660694
Short name T88
Test name
Test status
Simulation time 937869456 ps
CPU time 4.68 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:37 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921660694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2921660694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2954328200
Short name T76
Test name
Test status
Simulation time 869289748 ps
CPU time 3.5 seconds
Started Sep 24 09:37:10 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954328200 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.2954328200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4072288228
Short name T113
Test name
Test status
Simulation time 5288980342 ps
CPU time 26.19 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:59 PM UTC 24
Peak memory 220352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072288228 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4072288228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3026374884
Short name T2
Test name
Test status
Simulation time 76777882 ps
CPU time 0.82 seconds
Started Sep 24 09:37:30 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026374884 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3026374884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2846691732
Short name T4
Test name
Test status
Simulation time 106327577 ps
CPU time 1.18 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846691732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2846691732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1262889083
Short name T108
Test name
Test status
Simulation time 1226424557 ps
CPU time 5.56 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:44 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262889083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1262889083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2224069411
Short name T132
Test name
Test status
Simulation time 213905399 ps
CPU time 2.94 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 217704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224069411 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2224069411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.4001868114
Short name T115
Test name
Test status
Simulation time 1721205487 ps
CPU time 6.87 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:38:03 PM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001868114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4001868114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3548341863
Short name T50
Test name
Test status
Simulation time 1283245491 ps
CPU time 5.92 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:14 PM UTC 24
Peak memory 244160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548341863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3548341863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3478155148
Short name T101
Test name
Test status
Simulation time 125657048 ps
CPU time 1.81 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:17 PM UTC 24
Peak memory 217636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3478155148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w
ith_rand_reset.3478155148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3422039221
Short name T3
Test name
Test status
Simulation time 98238825 ps
CPU time 1.06 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422039221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3422039221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4217522839
Short name T133
Test name
Test status
Simulation time 883046074 ps
CPU time 3.28 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217522839 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.4217522839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2672484005
Short name T121
Test name
Test status
Simulation time 80159181 ps
CPU time 1.55 seconds
Started Sep 24 09:37:09 PM UTC 24
Finished Sep 24 09:37:12 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672484005 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2672484005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1788246982
Short name T1
Test name
Test status
Simulation time 205332941 ps
CPU time 1.01 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788246982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1788246982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2415015224
Short name T46
Test name
Test status
Simulation time 1957596290 ps
CPU time 8.63 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 244460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415015224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2415015224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.762082517
Short name T142
Test name
Test status
Simulation time 426319340 ps
CPU time 1.99 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 207760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762082517 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.762082517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3833316517
Short name T531
Test name
Test status
Simulation time 350663740 ps
CPU time 2.86 seconds
Started Sep 24 09:37:08 PM UTC 24
Finished Sep 24 09:37:12 PM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833316517 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3833316517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3983938696
Short name T536
Test name
Test status
Simulation time 483287752 ps
CPU time 7.64 seconds
Started Sep 24 09:37:08 PM UTC 24
Finished Sep 24 09:37:17 PM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983938696 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3983938696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.542736718
Short name T64
Test name
Test status
Simulation time 121368880 ps
CPU time 1.35 seconds
Started Sep 24 09:37:07 PM UTC 24
Finished Sep 24 09:37:09 PM UTC 24
Peak memory 208032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542736718 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.542736718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.1588406292
Short name T65
Test name
Test status
Simulation time 77873150 ps
CPU time 1.33 seconds
Started Sep 24 09:37:08 PM UTC 24
Finished Sep 24 09:37:10 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588406292 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1588406292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.228646233
Short name T72
Test name
Test status
Simulation time 259820426 ps
CPU time 3.2 seconds
Started Sep 24 09:37:06 PM UTC 24
Finished Sep 24 09:37:11 PM UTC 24
Peak memory 217900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228646233 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.228646233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2271572967
Short name T67
Test name
Test status
Simulation time 914630139 ps
CPU time 3.18 seconds
Started Sep 24 09:37:06 PM UTC 24
Finished Sep 24 09:37:11 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271572967 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.2271572967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2764074624
Short name T535
Test name
Test status
Simulation time 477617837 ps
CPU time 3.16 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:16 PM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764074624 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2764074624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1358415926
Short name T540
Test name
Test status
Simulation time 814879615 ps
CPU time 5.85 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 208480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358415926 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1358415926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4268261729
Short name T532
Test name
Test status
Simulation time 150277832 ps
CPU time 1.29 seconds
Started Sep 24 09:37:10 PM UTC 24
Finished Sep 24 09:37:13 PM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268261729 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4268261729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3438317342
Short name T75
Test name
Test status
Simulation time 205164265 ps
CPU time 1.63 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 217556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3438317342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w
ith_rand_reset.3438317342
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2958860751
Short name T122
Test name
Test status
Simulation time 81952576 ps
CPU time 1.4 seconds
Started Sep 24 09:37:11 PM UTC 24
Finished Sep 24 09:37:13 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958860751 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2958860751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3671810817
Short name T124
Test name
Test status
Simulation time 146165005 ps
CPU time 1.82 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671810817 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3671810817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1222170688
Short name T74
Test name
Test status
Simulation time 143157830 ps
CPU time 2.15 seconds
Started Sep 24 09:37:09 PM UTC 24
Finished Sep 24 09:37:12 PM UTC 24
Peak memory 217720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222170688 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1222170688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3914143244
Short name T566
Test name
Test status
Simulation time 136858274 ps
CPU time 1.56 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3914143244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_
with_rand_reset.3914143244
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3410394827
Short name T559
Test name
Test status
Simulation time 67732206 ps
CPU time 1.03 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410394827 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3410394827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4040743988
Short name T571
Test name
Test status
Simulation time 260946927 ps
CPU time 1.85 seconds
Started Sep 24 09:37:22 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040743988 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.4040743988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1689027597
Short name T106
Test name
Test status
Simulation time 281286229 ps
CPU time 2.19 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 217768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689027597 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1689027597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1370736169
Short name T572
Test name
Test status
Simulation time 798360773 ps
CPU time 3.39 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:26 PM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370736169 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1370736169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.830272991
Short name T568
Test name
Test status
Simulation time 109317693 ps
CPU time 1.34 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 217556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=830272991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_w
ith_rand_reset.830272991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.41986166
Short name T548
Test name
Test status
Simulation time 93492450 ps
CPU time 1.21 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41986166 -assert nopostproc +UVM_TESTNAME=rstmgr_
base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.41986166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1941118640
Short name T569
Test name
Test status
Simulation time 141619635 ps
CPU time 1.41 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941118640 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1941118640
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2528135412
Short name T570
Test name
Test status
Simulation time 96323703 ps
CPU time 1.58 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528135412 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2528135412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3941044262
Short name T574
Test name
Test status
Simulation time 118950863 ps
CPU time 1.18 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:26 PM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3941044262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_
with_rand_reset.3941044262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1194469542
Short name T567
Test name
Test status
Simulation time 73150641 ps
CPU time 1.11 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194469542 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1194469542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2982940323
Short name T576
Test name
Test status
Simulation time 230528896 ps
CPU time 1.59 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982940323 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.2982940323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.543868521
Short name T577
Test name
Test status
Simulation time 420205351 ps
CPU time 2.89 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 208812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543868521 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.543868521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.579249023
Short name T134
Test name
Test status
Simulation time 913743158 ps
CPU time 3.16 seconds
Started Sep 24 09:37:23 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579249023 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.579249023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.409415741
Short name T575
Test name
Test status
Simulation time 114578745 ps
CPU time 1.35 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 219544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=409415741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_w
ith_rand_reset.409415741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1308673027
Short name T573
Test name
Test status
Simulation time 71118136 ps
CPU time 0.97 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:26 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308673027 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1308673027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.594828088
Short name T578
Test name
Test status
Simulation time 286034895 ps
CPU time 1.9 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 207784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594828088 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.594828088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3592505836
Short name T585
Test name
Test status
Simulation time 384654849 ps
CPU time 3.16 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 217700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592505836 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3592505836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1840469959
Short name T579
Test name
Test status
Simulation time 93241948 ps
CPU time 1.05 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1840469959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_
with_rand_reset.1840469959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3701325733
Short name T112
Test name
Test status
Simulation time 76367463 ps
CPU time 1.2 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701325733 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3701325733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.491449936
Short name T590
Test name
Test status
Simulation time 282781806 ps
CPU time 1.91 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 207832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491449936 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.491449936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2653967748
Short name T589
Test name
Test status
Simulation time 202113610 ps
CPU time 3.18 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 217832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653967748 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2653967748
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1858416466
Short name T591
Test name
Test status
Simulation time 952291843 ps
CPU time 3.29 seconds
Started Sep 24 09:37:24 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858416466 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1858416466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1630811386
Short name T583
Test name
Test status
Simulation time 103024587 ps
CPU time 1.26 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1630811386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_
with_rand_reset.1630811386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2762272045
Short name T582
Test name
Test status
Simulation time 71732937 ps
CPU time 1.25 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762272045 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2762272045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3267467380
Short name T580
Test name
Test status
Simulation time 84278273 ps
CPU time 1.07 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 207836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267467380 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3267467380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.694859378
Short name T600
Test name
Test status
Simulation time 446608495 ps
CPU time 3.68 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 217812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694859378 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.694859378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2287563842
Short name T588
Test name
Test status
Simulation time 438916919 ps
CPU time 1.81 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287563842 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.2287563842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1762753939
Short name T586
Test name
Test status
Simulation time 123067080 ps
CPU time 1.32 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1762753939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_
with_rand_reset.1762753939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2466156894
Short name T581
Test name
Test status
Simulation time 67315545 ps
CPU time 1.06 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466156894 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2466156894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3550770264
Short name T587
Test name
Test status
Simulation time 137571308 ps
CPU time 1.48 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550770264 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.3550770264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3629799842
Short name T602
Test name
Test status
Simulation time 466907128 ps
CPU time 3.75 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 221784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629799842 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3629799842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2827071693
Short name T603
Test name
Test status
Simulation time 790746000 ps
CPU time 3.65 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827071693 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.2827071693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1436315623
Short name T593
Test name
Test status
Simulation time 118023296 ps
CPU time 1.17 seconds
Started Sep 24 09:37:27 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1436315623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_
with_rand_reset.1436315623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3250108777
Short name T584
Test name
Test status
Simulation time 60817155 ps
CPU time 0.89 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:28 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250108777 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3250108777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.33042268
Short name T599
Test name
Test status
Simulation time 279989860 ps
CPU time 1.82 seconds
Started Sep 24 09:37:27 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 217576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33042268 -assert nopostproc +UV
M_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.33042268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3940174861
Short name T592
Test name
Test status
Simulation time 221334085 ps
CPU time 2.04 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:29 PM UTC 24
Peak memory 225268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940174861 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3940174861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1050717490
Short name T143
Test name
Test status
Simulation time 1341574546 ps
CPU time 4.95 seconds
Started Sep 24 09:37:26 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050717490 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1050717490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4031918831
Short name T598
Test name
Test status
Simulation time 142856781 ps
CPU time 1.34 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4031918831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_
with_rand_reset.4031918831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1826051967
Short name T594
Test name
Test status
Simulation time 68915830 ps
CPU time 0.98 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826051967 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1826051967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.829967023
Short name T595
Test name
Test status
Simulation time 142321773 ps
CPU time 1.3 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829967023 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.829967023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2609208453
Short name T601
Test name
Test status
Simulation time 201566967 ps
CPU time 2.13 seconds
Started Sep 24 09:37:27 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 208896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609208453 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2609208453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3807545391
Short name T135
Test name
Test status
Simulation time 923623645 ps
CPU time 3.55 seconds
Started Sep 24 09:37:27 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807545391 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.3807545391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4132285970
Short name T606
Test name
Test status
Simulation time 214452531 ps
CPU time 1.43 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4132285970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_
with_rand_reset.4132285970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.819609663
Short name T596
Test name
Test status
Simulation time 61939920 ps
CPU time 1.05 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819609663 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.819609663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.366306301
Short name T597
Test name
Test status
Simulation time 127577194 ps
CPU time 1.24 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:30 PM UTC 24
Peak memory 207832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366306301 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.366306301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.4013368494
Short name T605
Test name
Test status
Simulation time 269360064 ps
CPU time 2.29 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013368494 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4013368494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1473153148
Short name T604
Test name
Test status
Simulation time 499407032 ps
CPU time 2.16 seconds
Started Sep 24 09:37:28 PM UTC 24
Finished Sep 24 09:37:31 PM UTC 24
Peak memory 217716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473153148 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1473153148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3289273419
Short name T537
Test name
Test status
Simulation time 360527079 ps
CPU time 2.56 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:17 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289273419 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3289273419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.697470709
Short name T543
Test name
Test status
Simulation time 489950382 ps
CPU time 6.43 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697470709 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.697470709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3952660021
Short name T533
Test name
Test status
Simulation time 104901063 ps
CPU time 1.43 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952660021 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3952660021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.418823476
Short name T123
Test name
Test status
Simulation time 77034250 ps
CPU time 1.38 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418823476 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.418823476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3534767094
Short name T126
Test name
Test status
Simulation time 210999524 ps
CPU time 1.81 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:16 PM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534767094 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.3534767094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3126071113
Short name T100
Test name
Test status
Simulation time 119289144 ps
CPU time 2.12 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:15 PM UTC 24
Peak memory 217648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126071113 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3126071113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4109005074
Short name T103
Test name
Test status
Simulation time 913957337 ps
CPU time 3.91 seconds
Started Sep 24 09:37:12 PM UTC 24
Finished Sep 24 09:37:17 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109005074 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.4109005074
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.223017373
Short name T542
Test name
Test status
Simulation time 348277568 ps
CPU time 2.53 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223017373 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.223017373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2891123051
Short name T538
Test name
Test status
Simulation time 271248643 ps
CPU time 3.54 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 217716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891123051 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2891123051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2259869550
Short name T534
Test name
Test status
Simulation time 121480702 ps
CPU time 1.11 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:16 PM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259869550 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2259869550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2396631149
Short name T105
Test name
Test status
Simulation time 180497851 ps
CPU time 1.9 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2396631149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w
ith_rand_reset.2396631149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.961818761
Short name T125
Test name
Test status
Simulation time 66567930 ps
CPU time 1.18 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:16 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961818761 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.961818761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3911188261
Short name T129
Test name
Test status
Simulation time 234278853 ps
CPU time 1.82 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911188261 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.3911188261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2024142127
Short name T102
Test name
Test status
Simulation time 175790940 ps
CPU time 2.11 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:17 PM UTC 24
Peak memory 217248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024142127 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2024142127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1502560444
Short name T104
Test name
Test status
Simulation time 772375522 ps
CPU time 3.66 seconds
Started Sep 24 09:37:14 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502560444 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.1502560444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1779668011
Short name T541
Test name
Test status
Simulation time 111458241 ps
CPU time 1.72 seconds
Started Sep 24 09:37:17 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779668011 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1779668011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2303809436
Short name T550
Test name
Test status
Simulation time 275988945 ps
CPU time 3.49 seconds
Started Sep 24 09:37:17 PM UTC 24
Finished Sep 24 09:37:21 PM UTC 24
Peak memory 208972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303809436 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2303809436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4176125604
Short name T539
Test name
Test status
Simulation time 93030271 ps
CPU time 1.29 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176125604 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4176125604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3395909737
Short name T139
Test name
Test status
Simulation time 114985138 ps
CPU time 1.31 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3395909737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w
ith_rand_reset.3395909737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1732708911
Short name T128
Test name
Test status
Simulation time 68818882 ps
CPU time 1.34 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732708911 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1732708911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2805257370
Short name T127
Test name
Test status
Simulation time 75829724 ps
CPU time 1.02 seconds
Started Sep 24 09:37:17 PM UTC 24
Finished Sep 24 09:37:19 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805257370 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.2805257370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1120352936
Short name T136
Test name
Test status
Simulation time 436700153 ps
CPU time 2.22 seconds
Started Sep 24 09:37:16 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120352936 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1120352936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3876018836
Short name T547
Test name
Test status
Simulation time 216024737 ps
CPU time 1.87 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:21 PM UTC 24
Peak memory 217556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3876018836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w
ith_rand_reset.3876018836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2445054902
Short name T544
Test name
Test status
Simulation time 77074163 ps
CPU time 1.08 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445054902 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2445054902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1855247257
Short name T546
Test name
Test status
Simulation time 282536983 ps
CPU time 1.8 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:21 PM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855247257 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.1855247257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1348604092
Short name T562
Test name
Test status
Simulation time 659068293 ps
CPU time 4.65 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 217840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348604092 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1348604092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2647674650
Short name T551
Test name
Test status
Simulation time 490574036 ps
CPU time 2.19 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:21 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647674650 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.2647674650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1126172609
Short name T549
Test name
Test status
Simulation time 136916315 ps
CPU time 1.76 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:21 PM UTC 24
Peak memory 217560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1126172609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w
ith_rand_reset.1126172609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1687627832
Short name T545
Test name
Test status
Simulation time 61370780 ps
CPU time 1.13 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687627832 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1687627832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3128120643
Short name T130
Test name
Test status
Simulation time 71290673 ps
CPU time 1.13 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:20 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128120643 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.3128120643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2489274688
Short name T138
Test name
Test status
Simulation time 182374902 ps
CPU time 2.79 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:22 PM UTC 24
Peak memory 217776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489274688 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2489274688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1023938615
Short name T140
Test name
Test status
Simulation time 951448084 ps
CPU time 3.73 seconds
Started Sep 24 09:37:18 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023938615 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.1023938615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3186469512
Short name T554
Test name
Test status
Simulation time 211708700 ps
CPU time 1.46 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:22 PM UTC 24
Peak memory 217560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3186469512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w
ith_rand_reset.3186469512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1336500326
Short name T552
Test name
Test status
Simulation time 61361110 ps
CPU time 1.1 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:22 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336500326 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1336500326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1140964862
Short name T555
Test name
Test status
Simulation time 240440572 ps
CPU time 1.71 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:22 PM UTC 24
Peak memory 207728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140964862 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.1140964862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3867240097
Short name T556
Test name
Test status
Simulation time 277113387 ps
CPU time 2.41 seconds
Started Sep 24 09:37:19 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 217688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867240097 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3867240097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2198838668
Short name T137
Test name
Test status
Simulation time 891993932 ps
CPU time 3.59 seconds
Started Sep 24 09:37:19 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198838668 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.2198838668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1306504975
Short name T564
Test name
Test status
Simulation time 178693334 ps
CPU time 2.03 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 217848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1306504975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w
ith_rand_reset.1306504975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3607369966
Short name T553
Test name
Test status
Simulation time 65285854 ps
CPU time 1.02 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:22 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607369966 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3607369966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2001975252
Short name T558
Test name
Test status
Simulation time 83244077 ps
CPU time 1.32 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001975252 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.2001975252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3276537028
Short name T565
Test name
Test status
Simulation time 201825415 ps
CPU time 3.45 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 225052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276537028 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3276537028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3735200605
Short name T141
Test name
Test status
Simulation time 866329670 ps
CPU time 3.13 seconds
Started Sep 24 09:37:20 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735200605 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.3735200605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1027055306
Short name T560
Test name
Test status
Simulation time 119998044 ps
CPU time 1.32 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1027055306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w
ith_rand_reset.1027055306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2078305077
Short name T557
Test name
Test status
Simulation time 68861160 ps
CPU time 1.11 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078305077 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2078305077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3429448161
Short name T561
Test name
Test status
Simulation time 115896829 ps
CPU time 1.34 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429448161 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.3429448161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.24404686
Short name T563
Test name
Test status
Simulation time 95022887 ps
CPU time 1.82 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:24 PM UTC 24
Peak memory 219680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24404686 -assert nopostproc +UVM_TESTNAME=rstmgr_bas
e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.24404686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.882186442
Short name T66
Test name
Test status
Simulation time 507325566 ps
CPU time 2.57 seconds
Started Sep 24 09:37:21 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882186442 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.882186442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.728120849
Short name T6
Test name
Test status
Simulation time 301081742 ps
CPU time 1.31 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:32 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728120849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.728120849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.3707334581
Short name T22
Test name
Test status
Simulation time 805866820 ps
CPU time 3.96 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707334581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3707334581
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2378934518
Short name T118
Test name
Test status
Simulation time 6007111246 ps
CPU time 21.4 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:53 PM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378934518 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2378934518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1016152235
Short name T62
Test name
Test status
Simulation time 504824593 ps
CPU time 2.92 seconds
Started Sep 24 09:37:29 PM UTC 24
Finished Sep 24 09:37:34 PM UTC 24
Peak memory 211208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016152235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1016152235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.704529668
Short name T25
Test name
Test status
Simulation time 70404099 ps
CPU time 1.06 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704529668 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.704529668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3305150013
Short name T14
Test name
Test status
Simulation time 307527103 ps
CPU time 1.11 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305150013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3305150013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3779148237
Short name T8
Test name
Test status
Simulation time 196286503 ps
CPU time 1.09 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779148237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3779148237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3802291813
Short name T79
Test name
Test status
Simulation time 16523876774 ps
CPU time 36.33 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:38:09 PM UTC 24
Peak memory 244264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802291813 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3802291813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1747411900
Short name T9
Test name
Test status
Simulation time 101776095 ps
CPU time 1.13 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747411900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1747411900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2952348071
Short name T10
Test name
Test status
Simulation time 192203417 ps
CPU time 1.35 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952348071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2952348071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1952545954
Short name T12
Test name
Test status
Simulation time 181204139 ps
CPU time 1.55 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952545954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1952545954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.11031809
Short name T186
Test name
Test status
Simulation time 67162173 ps
CPU time 1.13 seconds
Started Sep 24 09:37:49 PM UTC 24
Finished Sep 24 09:37:51 PM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11031809 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.11031809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.2281030287
Short name T48
Test name
Test status
Simulation time 2270471107 ps
CPU time 9.11 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:58 PM UTC 24
Peak memory 244548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281030287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2281030287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4034710847
Short name T185
Test name
Test status
Simulation time 301442749 ps
CPU time 1.62 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:51 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034710847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4034710847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.3764511531
Short name T182
Test name
Test status
Simulation time 126034769 ps
CPU time 1.12 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:50 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764511531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3764511531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.9471838
Short name T120
Test name
Test status
Simulation time 742575776 ps
CPU time 4.9 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:54 PM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9471838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.9471838
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4054151122
Short name T184
Test name
Test status
Simulation time 161368472 ps
CPU time 1.28 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:50 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054151122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4054151122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3506756806
Short name T177
Test name
Test status
Simulation time 113368746 ps
CPU time 1.51 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506756806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3506756806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.3109482642
Short name T270
Test name
Test status
Simulation time 7307625357 ps
CPU time 28.05 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:38:17 PM UTC 24
Peak memory 220580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109482642 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3109482642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2954929730
Short name T99
Test name
Test status
Simulation time 145499551 ps
CPU time 1.93 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:51 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954929730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2954929730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2037621635
Short name T183
Test name
Test status
Simulation time 68165688 ps
CPU time 1.2 seconds
Started Sep 24 09:37:48 PM UTC 24
Finished Sep 24 09:37:50 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037621635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2037621635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3534159540
Short name T153
Test name
Test status
Simulation time 80957708 ps
CPU time 1.04 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:37:53 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534159540 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3534159540
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.738468271
Short name T34
Test name
Test status
Simulation time 1964010528 ps
CPU time 8.29 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 243780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738468271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.738468271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3424107102
Short name T154
Test name
Test status
Simulation time 302273701 ps
CPU time 1.36 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:37:54 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424107102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3424107102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3567586798
Short name T187
Test name
Test status
Simulation time 175612413 ps
CPU time 1.32 seconds
Started Sep 24 09:37:49 PM UTC 24
Finished Sep 24 09:37:52 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567586798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3567586798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3547210879
Short name T157
Test name
Test status
Simulation time 777446559 ps
CPU time 4.15 seconds
Started Sep 24 09:37:49 PM UTC 24
Finished Sep 24 09:37:54 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547210879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3547210879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1878691567
Short name T152
Test name
Test status
Simulation time 95332423 ps
CPU time 1.29 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:37:53 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878691567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1878691567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.1780009060
Short name T188
Test name
Test status
Simulation time 192113497 ps
CPU time 1.57 seconds
Started Sep 24 09:37:49 PM UTC 24
Finished Sep 24 09:37:52 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780009060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1780009060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.159924982
Short name T144
Test name
Test status
Simulation time 5055614438 ps
CPU time 19.03 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:38:12 PM UTC 24
Peak memory 220396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159924982 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.159924982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1559020282
Short name T80
Test name
Test status
Simulation time 359736776 ps
CPU time 2.41 seconds
Started Sep 24 09:37:50 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559020282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1559020282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.3546504824
Short name T151
Test name
Test status
Simulation time 95950521 ps
CPU time 0.99 seconds
Started Sep 24 09:37:50 PM UTC 24
Finished Sep 24 09:37:53 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546504824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3546504824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.59861757
Short name T81
Test name
Test status
Simulation time 65068421 ps
CPU time 0.83 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59861757 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.59861757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.6109211
Short name T33
Test name
Test status
Simulation time 1277463452 ps
CPU time 6.22 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 244444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6109211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.6109211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4167882724
Short name T84
Test name
Test status
Simulation time 301525196 ps
CPU time 1.38 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167882724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4167882724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3914455686
Short name T156
Test name
Test status
Simulation time 225820710 ps
CPU time 1.16 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:37:54 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914455686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3914455686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.1419581539
Short name T198
Test name
Test status
Simulation time 1633501208 ps
CPU time 6.47 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 211600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419581539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1419581539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1207739973
Short name T82
Test name
Test status
Simulation time 96408806 ps
CPU time 1.14 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207739973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1207739973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3755156515
Short name T155
Test name
Test status
Simulation time 111564111 ps
CPU time 1.24 seconds
Started Sep 24 09:37:51 PM UTC 24
Finished Sep 24 09:37:54 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755156515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3755156515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.2195797476
Short name T342
Test name
Test status
Simulation time 13663843373 ps
CPU time 46.17 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:38:40 PM UTC 24
Peak memory 220264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195797476 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2195797476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.1090665663
Short name T161
Test name
Test status
Simulation time 528999257 ps
CPU time 2.8 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:37:56 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090665663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1090665663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.4089879043
Short name T83
Test name
Test status
Simulation time 213743258 ps
CPU time 1.77 seconds
Started Sep 24 09:37:52 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089879043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4089879043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2775934815
Short name T191
Test name
Test status
Simulation time 81732392 ps
CPU time 0.96 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:37:57 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775934815 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2775934815
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.1954900982
Short name T32
Test name
Test status
Simulation time 2443641172 ps
CPU time 9.39 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 244516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954900982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1954900982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3206251377
Short name T193
Test name
Test status
Simulation time 302162781 ps
CPU time 1.48 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:37:57 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206251377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3206251377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.1516507430
Short name T85
Test name
Test status
Simulation time 111820949 ps
CPU time 1.05 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:37:56 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516507430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1516507430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.737810465
Short name T203
Test name
Test status
Simulation time 993505416 ps
CPU time 5.45 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737810465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.737810465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.768054216
Short name T86
Test name
Test status
Simulation time 98165105 ps
CPU time 1.07 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:37:56 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768054216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.768054216
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.2022513608
Short name T87
Test name
Test status
Simulation time 192904603 ps
CPU time 1.4 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:37:56 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022513608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2022513608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.513477905
Short name T313
Test name
Test status
Simulation time 9485481447 ps
CPU time 37.49 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:38:34 PM UTC 24
Peak memory 220348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513477905 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.513477905
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3352649682
Short name T190
Test name
Test status
Simulation time 138818458 ps
CPU time 1.68 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:37:57 PM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352649682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3352649682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.1458852818
Short name T189
Test name
Test status
Simulation time 151539709 ps
CPU time 1.64 seconds
Started Sep 24 09:37:54 PM UTC 24
Finished Sep 24 09:37:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458852818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1458852818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.4001699584
Short name T194
Test name
Test status
Simulation time 60984780 ps
CPU time 1.17 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:37:59 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001699584 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4001699584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.4116950047
Short name T35
Test name
Test status
Simulation time 1981503556 ps
CPU time 7.68 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 243496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116950047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4116950047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3743077097
Short name T197
Test name
Test status
Simulation time 302750057 ps
CPU time 1.91 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 239236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743077097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3743077097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.775127748
Short name T192
Test name
Test status
Simulation time 164730839 ps
CPU time 1.01 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:37:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775127748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.775127748
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.647020736
Short name T196
Test name
Test status
Simulation time 153819457 ps
CPU time 1.87 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647020736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.647020736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.462477493
Short name T162
Test name
Test status
Simulation time 261331985 ps
CPU time 2.27 seconds
Started Sep 24 09:37:55 PM UTC 24
Finished Sep 24 09:37:58 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462477493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.462477493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3592834176
Short name T316
Test name
Test status
Simulation time 8918276140 ps
CPU time 37.8 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:38:36 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592834176 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3592834176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1665909794
Short name T163
Test name
Test status
Simulation time 514579642 ps
CPU time 2.69 seconds
Started Sep 24 09:37:56 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665909794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1665909794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.1205014696
Short name T195
Test name
Test status
Simulation time 280237625 ps
CPU time 1.81 seconds
Started Sep 24 09:37:56 PM UTC 24
Finished Sep 24 09:37:59 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205014696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1205014696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.3809927107
Short name T206
Test name
Test status
Simulation time 62897586 ps
CPU time 0.95 seconds
Started Sep 24 09:37:59 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809927107 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3809927107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.227517831
Short name T60
Test name
Test status
Simulation time 1275252687 ps
CPU time 7.47 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:07 PM UTC 24
Peak memory 244536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227517831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.227517831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3905625180
Short name T202
Test name
Test status
Simulation time 302404973 ps
CPU time 1.33 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905625180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3905625180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3486736685
Short name T201
Test name
Test status
Simulation time 189904890 ps
CPU time 1.55 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486736685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3486736685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.3657328029
Short name T116
Test name
Test status
Simulation time 1577965229 ps
CPU time 6.46 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657328029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3657328029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.968713685
Short name T204
Test name
Test status
Simulation time 180575922 ps
CPU time 1.67 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968713685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.968713685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.880241340
Short name T199
Test name
Test status
Simulation time 229566663 ps
CPU time 2.29 seconds
Started Sep 24 09:37:57 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880241340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.880241340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.314678740
Short name T297
Test name
Test status
Simulation time 5098811683 ps
CPU time 25.31 seconds
Started Sep 24 09:37:59 PM UTC 24
Finished Sep 24 09:38:26 PM UTC 24
Peak memory 220528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314678740 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.314678740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.1978526149
Short name T208
Test name
Test status
Simulation time 327280549 ps
CPU time 2.48 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:02 PM UTC 24
Peak memory 220240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978526149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1978526149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.3497855695
Short name T200
Test name
Test status
Simulation time 102286574 ps
CPU time 1.3 seconds
Started Sep 24 09:37:58 PM UTC 24
Finished Sep 24 09:38:00 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497855695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3497855695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.4068238469
Short name T214
Test name
Test status
Simulation time 67900000 ps
CPU time 0.98 seconds
Started Sep 24 09:38:02 PM UTC 24
Finished Sep 24 09:38:04 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068238469 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4068238469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.37845441
Short name T49
Test name
Test status
Simulation time 1269257650 ps
CPU time 6.54 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:09 PM UTC 24
Peak memory 244408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37845441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.37845441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2684326779
Short name T212
Test name
Test status
Simulation time 302530455 ps
CPU time 1.53 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:04 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684326779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2684326779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.4156561333
Short name T207
Test name
Test status
Simulation time 140207091 ps
CPU time 1.08 seconds
Started Sep 24 09:38:00 PM UTC 24
Finished Sep 24 09:38:02 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156561333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4156561333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3356209401
Short name T224
Test name
Test status
Simulation time 827740149 ps
CPU time 4.52 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356209401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3356209401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1748286516
Short name T211
Test name
Test status
Simulation time 142273820 ps
CPU time 1.37 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:03 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748286516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1748286516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3817856893
Short name T209
Test name
Test status
Simulation time 115203419 ps
CPU time 1.46 seconds
Started Sep 24 09:37:59 PM UTC 24
Finished Sep 24 09:38:02 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817856893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3817856893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.1419954724
Short name T363
Test name
Test status
Simulation time 16131406563 ps
CPU time 50.36 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:53 PM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419954724 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1419954724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.1916399656
Short name T213
Test name
Test status
Simulation time 262076956 ps
CPU time 1.81 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:04 PM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916399656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1916399656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3981050486
Short name T210
Test name
Test status
Simulation time 65739035 ps
CPU time 0.95 seconds
Started Sep 24 09:38:01 PM UTC 24
Finished Sep 24 09:38:03 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981050486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3981050486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.3532704991
Short name T216
Test name
Test status
Simulation time 70077834 ps
CPU time 1.11 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:05 PM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532704991 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3532704991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.3767120552
Short name T61
Test name
Test status
Simulation time 1276001010 ps
CPU time 6.33 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 244088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767120552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3767120552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2598679847
Short name T221
Test name
Test status
Simulation time 301649732 ps
CPU time 2.02 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 239988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598679847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2598679847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.4104303889
Short name T215
Test name
Test status
Simulation time 201871402 ps
CPU time 1.44 seconds
Started Sep 24 09:38:02 PM UTC 24
Finished Sep 24 09:38:05 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104303889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4104303889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.1584237786
Short name T240
Test name
Test status
Simulation time 1721463080 ps
CPU time 7.22 seconds
Started Sep 24 09:38:02 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584237786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1584237786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1481311506
Short name T220
Test name
Test status
Simulation time 179357497 ps
CPU time 1.86 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481311506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1481311506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3890792832
Short name T217
Test name
Test status
Simulation time 253197440 ps
CPU time 1.96 seconds
Started Sep 24 09:38:02 PM UTC 24
Finished Sep 24 09:38:05 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890792832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3890792832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.542345063
Short name T298
Test name
Test status
Simulation time 5517402389 ps
CPU time 22.42 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:26 PM UTC 24
Peak memory 219904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542345063 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.542345063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1011551634
Short name T222
Test name
Test status
Simulation time 266622510 ps
CPU time 2.21 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011551634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1011551634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.293820152
Short name T219
Test name
Test status
Simulation time 253942676 ps
CPU time 1.83 seconds
Started Sep 24 09:38:02 PM UTC 24
Finished Sep 24 09:38:05 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293820152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.293820152
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.1301497636
Short name T227
Test name
Test status
Simulation time 63483698 ps
CPU time 0.95 seconds
Started Sep 24 09:38:05 PM UTC 24
Finished Sep 24 09:38:07 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301497636 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1301497636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.3840076563
Short name T249
Test name
Test status
Simulation time 1954346031 ps
CPU time 7.64 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:13 PM UTC 24
Peak memory 243560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840076563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3840076563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3587743381
Short name T226
Test name
Test status
Simulation time 300906874 ps
CPU time 1.35 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:07 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587743381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3587743381
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2193461894
Short name T218
Test name
Test status
Simulation time 220901908 ps
CPU time 1.55 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:05 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193461894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2193461894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2918138583
Short name T241
Test name
Test status
Simulation time 1247257991 ps
CPU time 5.59 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918138583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2918138583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3683251557
Short name T225
Test name
Test status
Simulation time 97361163 ps
CPU time 1.15 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683251557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3683251557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.4096908446
Short name T205
Test name
Test status
Simulation time 200111538 ps
CPU time 1.81 seconds
Started Sep 24 09:38:03 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096908446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4096908446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.54098258
Short name T230
Test name
Test status
Simulation time 208692023 ps
CPU time 1.64 seconds
Started Sep 24 09:38:05 PM UTC 24
Finished Sep 24 09:38:08 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54098258 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.54098258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.139711476
Short name T229
Test name
Test status
Simulation time 338792499 ps
CPU time 2.54 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:08 PM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139711476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.139711476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.4237746951
Short name T223
Test name
Test status
Simulation time 95776352 ps
CPU time 1.1 seconds
Started Sep 24 09:38:04 PM UTC 24
Finished Sep 24 09:38:06 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237746951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4237746951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.1148299976
Short name T233
Test name
Test status
Simulation time 79079452 ps
CPU time 0.96 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148299976 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1148299976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1018378311
Short name T234
Test name
Test status
Simulation time 302574515 ps
CPU time 1.34 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018378311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1018378311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.372563372
Short name T228
Test name
Test status
Simulation time 130607651 ps
CPU time 1.16 seconds
Started Sep 24 09:38:06 PM UTC 24
Finished Sep 24 09:38:08 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372563372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.372563372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3619137151
Short name T145
Test name
Test status
Simulation time 1449830138 ps
CPU time 6.04 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619137151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3619137151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.858419830
Short name T239
Test name
Test status
Simulation time 147815137 ps
CPU time 1.87 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858419830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.858419830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.969553699
Short name T231
Test name
Test status
Simulation time 193698888 ps
CPU time 1.88 seconds
Started Sep 24 09:38:06 PM UTC 24
Finished Sep 24 09:38:08 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969553699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.969553699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.3067257206
Short name T294
Test name
Test status
Simulation time 3355018600 ps
CPU time 14.73 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:23 PM UTC 24
Peak memory 220400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067257206 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3067257206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.1264328166
Short name T243
Test name
Test status
Simulation time 322789090 ps
CPU time 2.66 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264328166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1264328166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.4255313836
Short name T235
Test name
Test status
Simulation time 148317190 ps
CPU time 1.52 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255313836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4255313836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2007015332
Short name T77
Test name
Test status
Simulation time 57954965 ps
CPU time 0.83 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007015332 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2007015332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.573430945
Short name T27
Test name
Test status
Simulation time 1960960582 ps
CPU time 8.12 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:42 PM UTC 24
Peak memory 244452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573430945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.573430945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4188668062
Short name T68
Test name
Test status
Simulation time 303024789 ps
CPU time 1.31 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188668062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4188668062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.939709917
Short name T11
Test name
Test status
Simulation time 84785237 ps
CPU time 0.9 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:33 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939709917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.939709917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1369654954
Short name T38
Test name
Test status
Simulation time 869667035 ps
CPU time 4.36 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369654954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1369654954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.1503656657
Short name T70
Test name
Test status
Simulation time 16639289109 ps
CPU time 26.75 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 244200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503656657 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1503656657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1444910419
Short name T23
Test name
Test status
Simulation time 186411554 ps
CPU time 1.28 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444910419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1444910419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1810452259
Short name T13
Test name
Test status
Simulation time 182110729 ps
CPU time 1.58 seconds
Started Sep 24 09:37:31 PM UTC 24
Finished Sep 24 09:37:34 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810452259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1810452259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.403752002
Short name T98
Test name
Test status
Simulation time 3179887715 ps
CPU time 15.17 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 211316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403752002 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.403752002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.1310561895
Short name T91
Test name
Test status
Simulation time 329871941 ps
CPU time 2.23 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:36 PM UTC 24
Peak memory 220272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310561895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1310561895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.3246170551
Short name T24
Test name
Test status
Simulation time 126828117 ps
CPU time 1.35 seconds
Started Sep 24 09:37:32 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246170551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3246170551
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.1207827045
Short name T244
Test name
Test status
Simulation time 55357882 ps
CPU time 0.99 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207827045 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1207827045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3445708280
Short name T274
Test name
Test status
Simulation time 1957122295 ps
CPU time 8.29 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:18 PM UTC 24
Peak memory 244516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445708280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3445708280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3321863912
Short name T246
Test name
Test status
Simulation time 301485211 ps
CPU time 1.39 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 239256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321863912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3321863912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.4190401592
Short name T236
Test name
Test status
Simulation time 155782198 ps
CPU time 1.11 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190401592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4190401592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.193426983
Short name T259
Test name
Test status
Simulation time 1281288128 ps
CPU time 6.01 seconds
Started Sep 24 09:38:08 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 211608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193426983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.193426983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2334152304
Short name T238
Test name
Test status
Simulation time 96201444 ps
CPU time 1.23 seconds
Started Sep 24 09:38:08 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334152304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2334152304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.3225362463
Short name T242
Test name
Test status
Simulation time 247858389 ps
CPU time 2.23 seconds
Started Sep 24 09:38:07 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225362463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3225362463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.912060328
Short name T358
Test name
Test status
Simulation time 9857577311 ps
CPU time 39.05 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:50 PM UTC 24
Peak memory 220524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912060328 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.912060328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.2703098602
Short name T245
Test name
Test status
Simulation time 154197262 ps
CPU time 2.39 seconds
Started Sep 24 09:38:08 PM UTC 24
Finished Sep 24 09:38:11 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703098602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2703098602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.4275971118
Short name T237
Test name
Test status
Simulation time 67067531 ps
CPU time 1.11 seconds
Started Sep 24 09:38:08 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275971118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4275971118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.2339208834
Short name T252
Test name
Test status
Simulation time 69900145 ps
CPU time 1.11 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:13 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339208834 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2339208834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.2087269571
Short name T281
Test name
Test status
Simulation time 1271837878 ps
CPU time 6.93 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 244476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087269571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2087269571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1558994479
Short name T256
Test name
Test status
Simulation time 301079393 ps
CPU time 1.99 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:14 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558994479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1558994479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.689851531
Short name T247
Test name
Test status
Simulation time 118957635 ps
CPU time 1.03 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:12 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689851531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.689851531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.4172896725
Short name T265
Test name
Test status
Simulation time 863572000 ps
CPU time 5.23 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:16 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172896725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4172896725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3826687643
Short name T253
Test name
Test status
Simulation time 101742302 ps
CPU time 1.48 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:14 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826687643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3826687643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.499919520
Short name T248
Test name
Test status
Simulation time 249284698 ps
CPU time 1.63 seconds
Started Sep 24 09:38:09 PM UTC 24
Finished Sep 24 09:38:12 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499919520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.499919520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2404931696
Short name T338
Test name
Test status
Simulation time 7874345717 ps
CPU time 26.26 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:39 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404931696 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2404931696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2215010534
Short name T254
Test name
Test status
Simulation time 123360409 ps
CPU time 1.66 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:14 PM UTC 24
Peak memory 219488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215010534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2215010534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3737857063
Short name T250
Test name
Test status
Simulation time 114827684 ps
CPU time 1.14 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:13 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737857063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3737857063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2856001276
Short name T258
Test name
Test status
Simulation time 73374430 ps
CPU time 0.91 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856001276 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2856001276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.2861281622
Short name T283
Test name
Test status
Simulation time 1271544043 ps
CPU time 6.06 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:20 PM UTC 24
Peak memory 244408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861281622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2861281622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1481216789
Short name T260
Test name
Test status
Simulation time 313319376 ps
CPU time 1.3 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481216789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1481216789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.57902396
Short name T251
Test name
Test status
Simulation time 98116281 ps
CPU time 0.87 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:13 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57902396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.57902396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.116243949
Short name T147
Test name
Test status
Simulation time 1684508341 ps
CPU time 6.17 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116243949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.116243949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1863448987
Short name T262
Test name
Test status
Simulation time 103822121 ps
CPU time 1.41 seconds
Started Sep 24 09:38:12 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863448987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1863448987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.128431153
Short name T255
Test name
Test status
Simulation time 116874049 ps
CPU time 1.52 seconds
Started Sep 24 09:38:11 PM UTC 24
Finished Sep 24 09:38:14 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128431153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.128431153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.4056354329
Short name T361
Test name
Test status
Simulation time 11918467488 ps
CPU time 37.93 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:52 PM UTC 24
Peak memory 220336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056354329 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4056354329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.354489600
Short name T266
Test name
Test status
Simulation time 401735905 ps
CPU time 2.31 seconds
Started Sep 24 09:38:12 PM UTC 24
Finished Sep 24 09:38:16 PM UTC 24
Peak memory 211084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354489600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.354489600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.4261056377
Short name T261
Test name
Test status
Simulation time 169708362 ps
CPU time 1.4 seconds
Started Sep 24 09:38:12 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261056377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4261056377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.3248075887
Short name T267
Test name
Test status
Simulation time 83026293 ps
CPU time 0.88 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:17 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248075887 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3248075887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3143089738
Short name T295
Test name
Test status
Simulation time 1994001794 ps
CPU time 8.32 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:24 PM UTC 24
Peak memory 244608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143089738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3143089738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3482212825
Short name T271
Test name
Test status
Simulation time 302157028 ps
CPU time 1.68 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:17 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482212825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3482212825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.2384639307
Short name T257
Test name
Test status
Simulation time 113568833 ps
CPU time 0.87 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 210184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384639307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2384639307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3167706389
Short name T148
Test name
Test status
Simulation time 1566746488 ps
CPU time 5.97 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:20 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167706389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3167706389
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2936564630
Short name T269
Test name
Test status
Simulation time 140527658 ps
CPU time 1.41 seconds
Started Sep 24 09:38:14 PM UTC 24
Finished Sep 24 09:38:17 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936564630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2936564630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3582856751
Short name T264
Test name
Test status
Simulation time 264081536 ps
CPU time 1.79 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:16 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582856751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3582856751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.1051638140
Short name T340
Test name
Test status
Simulation time 5521032395 ps
CPU time 23.86 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:40 PM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051638140 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1051638140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.1843414952
Short name T280
Test name
Test status
Simulation time 370900035 ps
CPU time 3.47 seconds
Started Sep 24 09:38:14 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843414952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1843414952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.2399569763
Short name T263
Test name
Test status
Simulation time 98152017 ps
CPU time 1.31 seconds
Started Sep 24 09:38:13 PM UTC 24
Finished Sep 24 09:38:15 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399569763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2399569763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.802672823
Short name T275
Test name
Test status
Simulation time 81530569 ps
CPU time 1.16 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802672823 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.802672823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.720892428
Short name T51
Test name
Test status
Simulation time 1270289246 ps
CPU time 5.97 seconds
Started Sep 24 09:38:16 PM UTC 24
Finished Sep 24 09:38:24 PM UTC 24
Peak memory 243728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720892428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.720892428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.395367117
Short name T277
Test name
Test status
Simulation time 302023602 ps
CPU time 1.38 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 239200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395367117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.395367117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.154636833
Short name T268
Test name
Test status
Simulation time 87065771 ps
CPU time 0.9 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:17 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154636833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.154636833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.300564345
Short name T289
Test name
Test status
Simulation time 1008837847 ps
CPU time 5.78 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300564345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.300564345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1121214941
Short name T279
Test name
Test status
Simulation time 180414730 ps
CPU time 1.49 seconds
Started Sep 24 09:38:16 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121214941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1121214941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.1013776668
Short name T272
Test name
Test status
Simulation time 197987610 ps
CPU time 1.56 seconds
Started Sep 24 09:38:15 PM UTC 24
Finished Sep 24 09:38:18 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013776668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1013776668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3727184404
Short name T293
Test name
Test status
Simulation time 1101163337 ps
CPU time 5.58 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:23 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727184404 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3727184404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.41260227
Short name T284
Test name
Test status
Simulation time 352405769 ps
CPU time 2.74 seconds
Started Sep 24 09:38:16 PM UTC 24
Finished Sep 24 09:38:20 PM UTC 24
Peak memory 211084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41260227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.41260227
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.3018635214
Short name T273
Test name
Test status
Simulation time 120573853 ps
CPU time 1.01 seconds
Started Sep 24 09:38:16 PM UTC 24
Finished Sep 24 09:38:18 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018635214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3018635214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.765814209
Short name T288
Test name
Test status
Simulation time 73028342 ps
CPU time 1 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765814209 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.765814209
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.1034355664
Short name T300
Test name
Test status
Simulation time 2248334347 ps
CPU time 7.88 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:27 PM UTC 24
Peak memory 244512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034355664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1034355664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1283977148
Short name T287
Test name
Test status
Simulation time 301952535 ps
CPU time 1.53 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:21 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283977148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1283977148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2962711619
Short name T278
Test name
Test status
Simulation time 86491856 ps
CPU time 1.21 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962711619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2962711619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.931816833
Short name T292
Test name
Test status
Simulation time 1220953881 ps
CPU time 4.86 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:23 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931816833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.931816833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.288052524
Short name T285
Test name
Test status
Simulation time 104453997 ps
CPU time 1.43 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:21 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288052524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.288052524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1725517616
Short name T282
Test name
Test status
Simulation time 252331900 ps
CPU time 1.79 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725517616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1725517616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.4073099178
Short name T150
Test name
Test status
Simulation time 4347651613 ps
CPU time 15.56 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:35 PM UTC 24
Peak memory 220340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073099178 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4073099178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.1941135092
Short name T290
Test name
Test status
Simulation time 383570012 ps
CPU time 2.46 seconds
Started Sep 24 09:38:18 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941135092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1941135092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3332496303
Short name T276
Test name
Test status
Simulation time 107235841 ps
CPU time 1.1 seconds
Started Sep 24 09:38:17 PM UTC 24
Finished Sep 24 09:38:19 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332496303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3332496303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.4185514223
Short name T305
Test name
Test status
Simulation time 68359634 ps
CPU time 1.14 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185514223 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4185514223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.938597734
Short name T343
Test name
Test status
Simulation time 2446255700 ps
CPU time 9.54 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:41 PM UTC 24
Peak memory 244360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938597734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.938597734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2813316745
Short name T309
Test name
Test status
Simulation time 301491566 ps
CPU time 1.5 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813316745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2813316745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3591752165
Short name T232
Test name
Test status
Simulation time 104525624 ps
CPU time 0.96 seconds
Started Sep 24 09:38:19 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591752165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3591752165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2160350900
Short name T296
Test name
Test status
Simulation time 929797736 ps
CPU time 4.74 seconds
Started Sep 24 09:38:19 PM UTC 24
Finished Sep 24 09:38:26 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160350900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2160350900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3630289298
Short name T311
Test name
Test status
Simulation time 183623883 ps
CPU time 1.73 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630289298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3630289298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.1398370316
Short name T286
Test name
Test status
Simulation time 121147886 ps
CPU time 1.31 seconds
Started Sep 24 09:38:19 PM UTC 24
Finished Sep 24 09:38:21 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398370316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1398370316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.2727355989
Short name T315
Test name
Test status
Simulation time 817327568 ps
CPU time 4.12 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:36 PM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727355989 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2727355989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.350743829
Short name T308
Test name
Test status
Simulation time 130438515 ps
CPU time 1.71 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350743829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.350743829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.2741064736
Short name T291
Test name
Test status
Simulation time 121693056 ps
CPU time 1.22 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741064736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2741064736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.1355616254
Short name T329
Test name
Test status
Simulation time 73439983 ps
CPU time 1.12 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355616254 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1355616254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.3591155320
Short name T350
Test name
Test status
Simulation time 2441434984 ps
CPU time 7.95 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:44 PM UTC 24
Peak memory 244476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591155320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3591155320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1385759493
Short name T330
Test name
Test status
Simulation time 301824903 ps
CPU time 1.24 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385759493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1385759493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1025055012
Short name T307
Test name
Test status
Simulation time 193665822 ps
CPU time 1.23 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025055012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1025055012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.139694169
Short name T339
Test name
Test status
Simulation time 1922376731 ps
CPU time 7.41 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:39 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139694169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.139694169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3018091018
Short name T326
Test name
Test status
Simulation time 150666032 ps
CPU time 1.12 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018091018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3018091018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1864760820
Short name T306
Test name
Test status
Simulation time 129775364 ps
CPU time 1.2 seconds
Started Sep 24 09:38:20 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864760820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1864760820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.2594609794
Short name T332
Test name
Test status
Simulation time 150746212 ps
CPU time 1.33 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594609794 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2594609794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.706207055
Short name T335
Test name
Test status
Simulation time 131485283 ps
CPU time 1.87 seconds
Started Sep 24 09:38:22 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 219488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706207055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.706207055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.2053644282
Short name T310
Test name
Test status
Simulation time 144245155 ps
CPU time 1.25 seconds
Started Sep 24 09:38:21 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053644282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2053644282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.602676167
Short name T324
Test name
Test status
Simulation time 77821502 ps
CPU time 0.88 seconds
Started Sep 24 09:38:25 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602676167 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.602676167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2473043756
Short name T302
Test name
Test status
Simulation time 1264966016 ps
CPU time 5.41 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:31 PM UTC 24
Peak memory 253968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473043756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2473043756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1759917391
Short name T331
Test name
Test status
Simulation time 301245712 ps
CPU time 1.39 seconds
Started Sep 24 09:38:25 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759917391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1759917391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.425331975
Short name T317
Test name
Test status
Simulation time 133116724 ps
CPU time 0.86 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:36 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425331975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.425331975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.812590339
Short name T301
Test name
Test status
Simulation time 762503357 ps
CPU time 3.52 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:29 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812590339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.812590339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3590321095
Short name T320
Test name
Test status
Simulation time 185315264 ps
CPU time 1.12 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590321095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3590321095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3261527441
Short name T312
Test name
Test status
Simulation time 254784407 ps
CPU time 1.74 seconds
Started Sep 24 09:38:23 PM UTC 24
Finished Sep 24 09:38:33 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261527441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3261527441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2517456053
Short name T420
Test name
Test status
Simulation time 12551957279 ps
CPU time 44.36 seconds
Started Sep 24 09:38:25 PM UTC 24
Finished Sep 24 09:39:21 PM UTC 24
Peak memory 220472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517456053 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2517456053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.2529262102
Short name T327
Test name
Test status
Simulation time 129071747 ps
CPU time 1.59 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 219200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529262102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2529262102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.2482295883
Short name T299
Test name
Test status
Simulation time 99244287 ps
CPU time 1.01 seconds
Started Sep 24 09:38:24 PM UTC 24
Finished Sep 24 09:38:27 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482295883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2482295883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1089934600
Short name T345
Test name
Test status
Simulation time 72983171 ps
CPU time 0.75 seconds
Started Sep 24 09:38:33 PM UTC 24
Finished Sep 24 09:38:41 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089934600 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1089934600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.1171887058
Short name T336
Test name
Test status
Simulation time 2275169340 ps
CPU time 7.24 seconds
Started Sep 24 09:38:30 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 244128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171887058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1171887058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.664982525
Short name T328
Test name
Test status
Simulation time 301787660 ps
CPU time 1.32 seconds
Started Sep 24 09:38:32 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664982525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.664982525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.1477117483
Short name T344
Test name
Test status
Simulation time 87455782 ps
CPU time 0.75 seconds
Started Sep 24 09:38:26 PM UTC 24
Finished Sep 24 09:38:41 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477117483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1477117483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.2861659571
Short name T318
Test name
Test status
Simulation time 1085585184 ps
CPU time 5 seconds
Started Sep 24 09:38:27 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861659571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2861659571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1208151196
Short name T303
Test name
Test status
Simulation time 144736283 ps
CPU time 1.17 seconds
Started Sep 24 09:38:29 PM UTC 24
Finished Sep 24 09:38:32 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208151196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1208151196
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.373221235
Short name T333
Test name
Test status
Simulation time 248158426 ps
CPU time 1.59 seconds
Started Sep 24 09:38:25 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373221235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.373221235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.2863600008
Short name T351
Test name
Test status
Simulation time 1251413019 ps
CPU time 5.23 seconds
Started Sep 24 09:38:33 PM UTC 24
Finished Sep 24 09:38:46 PM UTC 24
Peak memory 220468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863600008 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2863600008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1666712930
Short name T314
Test name
Test status
Simulation time 347691658 ps
CPU time 2.43 seconds
Started Sep 24 09:38:27 PM UTC 24
Finished Sep 24 09:38:34 PM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666712930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1666712930
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3401742627
Short name T304
Test name
Test status
Simulation time 79916406 ps
CPU time 0.8 seconds
Started Sep 24 09:38:27 PM UTC 24
Finished Sep 24 09:38:32 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401742627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3401742627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1416116406
Short name T37
Test name
Test status
Simulation time 79202751 ps
CPU time 0.99 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416116406 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1416116406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3473538587
Short name T47
Test name
Test status
Simulation time 1961551714 ps
CPU time 9.31 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 244224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473538587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3473538587
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2254534793
Short name T45
Test name
Test status
Simulation time 302331895 ps
CPU time 1.4 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:37 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254534793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2254534793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.676693156
Short name T15
Test name
Test status
Simulation time 195953145 ps
CPU time 1.15 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:36 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676693156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.676693156
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.2179565334
Short name T107
Test name
Test status
Simulation time 1375916964 ps
CPU time 6.1 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179565334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2179565334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.432202512
Short name T78
Test name
Test status
Simulation time 16551284105 ps
CPU time 26.93 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:38:04 PM UTC 24
Peak memory 243624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432202512 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.432202512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4125104912
Short name T90
Test name
Test status
Simulation time 155192906 ps
CPU time 1.36 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:36 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125104912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4125104912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1575414754
Short name T89
Test name
Test status
Simulation time 189532037 ps
CPU time 1.51 seconds
Started Sep 24 09:37:33 PM UTC 24
Finished Sep 24 09:37:35 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575414754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1575414754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2551266720
Short name T117
Test name
Test status
Simulation time 6220285720 ps
CPU time 31.06 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:38:07 PM UTC 24
Peak memory 220336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551266720 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2551266720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.2441389546
Short name T36
Test name
Test status
Simulation time 382775460 ps
CPU time 2.27 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:37 PM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441389546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2441389546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3836571505
Short name T92
Test name
Test status
Simulation time 141161036 ps
CPU time 1.31 seconds
Started Sep 24 09:37:34 PM UTC 24
Finished Sep 24 09:37:36 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836571505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3836571505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1095214273
Short name T346
Test name
Test status
Simulation time 85243767 ps
CPU time 0.96 seconds
Started Sep 24 09:38:36 PM UTC 24
Finished Sep 24 09:38:41 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095214273 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1095214273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.894148452
Short name T349
Test name
Test status
Simulation time 1975089949 ps
CPU time 7.19 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:43 PM UTC 24
Peak memory 244404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894148452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.894148452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1608703697
Short name T325
Test name
Test status
Simulation time 302870106 ps
CPU time 1.16 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608703697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1608703697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2656261125
Short name T319
Test name
Test status
Simulation time 174653848 ps
CPU time 1.02 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656261125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2656261125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.1712778135
Short name T341
Test name
Test status
Simulation time 965423110 ps
CPU time 4.13 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:40 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712778135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1712778135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4060438883
Short name T321
Test name
Test status
Simulation time 149480363 ps
CPU time 1.05 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060438883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4060438883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.727806781
Short name T323
Test name
Test status
Simulation time 117855615 ps
CPU time 1.27 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727806781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.727806781
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.425403539
Short name T381
Test name
Test status
Simulation time 8917153383 ps
CPU time 28.77 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:39:05 PM UTC 24
Peak memory 220320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425403539 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.425403539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.4034183723
Short name T334
Test name
Test status
Simulation time 307910080 ps
CPU time 2.12 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 220032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034183723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4034183723
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.687369526
Short name T322
Test name
Test status
Simulation time 101149258 ps
CPU time 1.19 seconds
Started Sep 24 09:38:35 PM UTC 24
Finished Sep 24 09:38:37 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687369526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.687369526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.3108454192
Short name T380
Test name
Test status
Simulation time 2269303162 ps
CPU time 8.71 seconds
Started Sep 24 09:38:38 PM UTC 24
Finished Sep 24 09:39:05 PM UTC 24
Peak memory 244608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108454192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3108454192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.945355468
Short name T347
Test name
Test status
Simulation time 166406928 ps
CPU time 0.95 seconds
Started Sep 24 09:38:36 PM UTC 24
Finished Sep 24 09:38:41 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945355468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.945355468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1368581466
Short name T362
Test name
Test status
Simulation time 2083635899 ps
CPU time 7.47 seconds
Started Sep 24 09:38:38 PM UTC 24
Finished Sep 24 09:38:53 PM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368581466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1368581466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3480023201
Short name T348
Test name
Test status
Simulation time 187375056 ps
CPU time 1.44 seconds
Started Sep 24 09:38:36 PM UTC 24
Finished Sep 24 09:38:42 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480023201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3480023201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.614890095
Short name T523
Test name
Test status
Simulation time 9515028631 ps
CPU time 35.21 seconds
Started Sep 24 09:38:38 PM UTC 24
Finished Sep 24 09:39:49 PM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614890095 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.614890095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1186602841
Short name T354
Test name
Test status
Simulation time 137360909 ps
CPU time 1.53 seconds
Started Sep 24 09:38:38 PM UTC 24
Finished Sep 24 09:38:47 PM UTC 24
Peak memory 219488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186602841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1186602841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.2903151436
Short name T352
Test name
Test status
Simulation time 142360479 ps
CPU time 1.15 seconds
Started Sep 24 09:38:38 PM UTC 24
Finished Sep 24 09:38:46 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903151436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2903151436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.3998939392
Short name T373
Test name
Test status
Simulation time 71908377 ps
CPU time 0.79 seconds
Started Sep 24 09:38:43 PM UTC 24
Finished Sep 24 09:39:02 PM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998939392 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3998939392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.732152446
Short name T409
Test name
Test status
Simulation time 1277287545 ps
CPU time 5 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:17 PM UTC 24
Peak memory 244480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732152446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.732152446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3275046230
Short name T375
Test name
Test status
Simulation time 302039665 ps
CPU time 1.2 seconds
Started Sep 24 09:38:43 PM UTC 24
Finished Sep 24 09:39:03 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275046230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3275046230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2681264176
Short name T383
Test name
Test status
Simulation time 170952959 ps
CPU time 0.87 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:06 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681264176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2681264176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.830876484
Short name T406
Test name
Test status
Simulation time 733533695 ps
CPU time 3.77 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:16 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830876484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.830876484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1595892105
Short name T398
Test name
Test status
Simulation time 110406552 ps
CPU time 1.05 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:13 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595892105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1595892105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.2484775458
Short name T353
Test name
Test status
Simulation time 188701876 ps
CPU time 1.29 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:38:46 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484775458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2484775458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.4253475827
Short name T457
Test name
Test status
Simulation time 8927314973 ps
CPU time 27.97 seconds
Started Sep 24 09:38:43 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253475827 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4253475827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.3797682451
Short name T385
Test name
Test status
Simulation time 108608029 ps
CPU time 1.3 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:07 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797682451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3797682451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.2196737496
Short name T384
Test name
Test status
Simulation time 122273947 ps
CPU time 1.05 seconds
Started Sep 24 09:38:41 PM UTC 24
Finished Sep 24 09:39:06 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196737496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2196737496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.2143697970
Short name T413
Test name
Test status
Simulation time 77322223 ps
CPU time 0.8 seconds
Started Sep 24 09:38:46 PM UTC 24
Finished Sep 24 09:39:18 PM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143697970 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2143697970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.1488443209
Short name T359
Test name
Test status
Simulation time 1266159211 ps
CPU time 4.96 seconds
Started Sep 24 09:38:44 PM UTC 24
Finished Sep 24 09:38:51 PM UTC 24
Peak memory 243900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488443209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1488443209
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1569821376
Short name T374
Test name
Test status
Simulation time 139946084 ps
CPU time 0.83 seconds
Started Sep 24 09:38:43 PM UTC 24
Finished Sep 24 09:39:03 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569821376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1569821376
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.1851161282
Short name T386
Test name
Test status
Simulation time 1377162729 ps
CPU time 5.34 seconds
Started Sep 24 09:38:44 PM UTC 24
Finished Sep 24 09:39:07 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851161282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1851161282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4101134948
Short name T356
Test name
Test status
Simulation time 156813827 ps
CPU time 1.12 seconds
Started Sep 24 09:38:44 PM UTC 24
Finished Sep 24 09:38:47 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101134948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4101134948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.3457132510
Short name T376
Test name
Test status
Simulation time 254485006 ps
CPU time 1.46 seconds
Started Sep 24 09:38:43 PM UTC 24
Finished Sep 24 09:39:03 PM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457132510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3457132510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1698691194
Short name T377
Test name
Test status
Simulation time 2424505825 ps
CPU time 7.12 seconds
Started Sep 24 09:38:45 PM UTC 24
Finished Sep 24 09:39:03 PM UTC 24
Peak memory 220404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698691194 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1698691194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.769109194
Short name T357
Test name
Test status
Simulation time 467077124 ps
CPU time 2.5 seconds
Started Sep 24 09:38:44 PM UTC 24
Finished Sep 24 09:38:48 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769109194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.769109194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.529811096
Short name T355
Test name
Test status
Simulation time 163165749 ps
CPU time 1.16 seconds
Started Sep 24 09:38:44 PM UTC 24
Finished Sep 24 09:38:47 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529811096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.529811096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.3248020462
Short name T370
Test name
Test status
Simulation time 82035144 ps
CPU time 0.77 seconds
Started Sep 24 09:38:53 PM UTC 24
Finished Sep 24 09:39:02 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248020462 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3248020462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.132578962
Short name T369
Test name
Test status
Simulation time 2457169056 ps
CPU time 8.86 seconds
Started Sep 24 09:38:50 PM UTC 24
Finished Sep 24 09:39:00 PM UTC 24
Peak memory 243792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132578962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.132578962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3466773256
Short name T400
Test name
Test status
Simulation time 301409986 ps
CPU time 1.24 seconds
Started Sep 24 09:38:51 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 239180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466773256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3466773256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.1143427210
Short name T364
Test name
Test status
Simulation time 78447049 ps
CPU time 0.76 seconds
Started Sep 24 09:38:48 PM UTC 24
Finished Sep 24 09:38:57 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143427210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1143427210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.1094100188
Short name T382
Test name
Test status
Simulation time 788502991 ps
CPU time 3.41 seconds
Started Sep 24 09:38:48 PM UTC 24
Finished Sep 24 09:39:05 PM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094100188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1094100188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.78474760
Short name T360
Test name
Test status
Simulation time 107079746 ps
CPU time 0.96 seconds
Started Sep 24 09:38:49 PM UTC 24
Finished Sep 24 09:38:52 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78474760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.78474760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.1849478676
Short name T365
Test name
Test status
Simulation time 124694942 ps
CPU time 1.12 seconds
Started Sep 24 09:38:48 PM UTC 24
Finished Sep 24 09:38:57 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849478676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1849478676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.1602875133
Short name T437
Test name
Test status
Simulation time 3623180382 ps
CPU time 11.88 seconds
Started Sep 24 09:38:51 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 220280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602875133 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1602875133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.3049172387
Short name T367
Test name
Test status
Simulation time 267160684 ps
CPU time 1.7 seconds
Started Sep 24 09:38:48 PM UTC 24
Finished Sep 24 09:38:58 PM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049172387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3049172387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2619170324
Short name T366
Test name
Test status
Simulation time 231789446 ps
CPU time 1.3 seconds
Started Sep 24 09:38:48 PM UTC 24
Finished Sep 24 09:38:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619170324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2619170324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.313785259
Short name T399
Test name
Test status
Simulation time 64574341 ps
CPU time 0.75 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313785259 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.313785259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.2153357778
Short name T387
Test name
Test status
Simulation time 1958049606 ps
CPU time 6.35 seconds
Started Sep 24 09:38:59 PM UTC 24
Finished Sep 24 09:39:08 PM UTC 24
Peak memory 253964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153357778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2153357778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1347146363
Short name T372
Test name
Test status
Simulation time 301113232 ps
CPU time 1.14 seconds
Started Sep 24 09:39:00 PM UTC 24
Finished Sep 24 09:39:02 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347146363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1347146363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.846861460
Short name T402
Test name
Test status
Simulation time 119942540 ps
CPU time 0.75 seconds
Started Sep 24 09:38:54 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846861460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.846861460
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1171475651
Short name T368
Test name
Test status
Simulation time 703206651 ps
CPU time 3.43 seconds
Started Sep 24 09:38:54 PM UTC 24
Finished Sep 24 09:39:00 PM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171475651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1171475651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3054311138
Short name T378
Test name
Test status
Simulation time 168819768 ps
CPU time 1.21 seconds
Started Sep 24 09:38:58 PM UTC 24
Finished Sep 24 09:39:03 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054311138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3054311138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3937937329
Short name T371
Test name
Test status
Simulation time 196488927 ps
CPU time 1.35 seconds
Started Sep 24 09:38:53 PM UTC 24
Finished Sep 24 09:39:02 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937937329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3937937329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.1572170006
Short name T504
Test name
Test status
Simulation time 8706009847 ps
CPU time 30.88 seconds
Started Sep 24 09:39:02 PM UTC 24
Finished Sep 24 09:39:44 PM UTC 24
Peak memory 220528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572170006 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1572170006
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1520127349
Short name T379
Test name
Test status
Simulation time 348609429 ps
CPU time 1.99 seconds
Started Sep 24 09:38:58 PM UTC 24
Finished Sep 24 09:39:04 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520127349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1520127349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.81281727
Short name T397
Test name
Test status
Simulation time 119370314 ps
CPU time 0.89 seconds
Started Sep 24 09:38:58 PM UTC 24
Finished Sep 24 09:39:13 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81281727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.81281727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.939369335
Short name T410
Test name
Test status
Simulation time 80916036 ps
CPU time 0.74 seconds
Started Sep 24 09:39:06 PM UTC 24
Finished Sep 24 09:39:17 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939369335 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.939369335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3309536337
Short name T440
Test name
Test status
Simulation time 2434221401 ps
CPU time 8.98 seconds
Started Sep 24 09:39:06 PM UTC 24
Finished Sep 24 09:39:26 PM UTC 24
Peak memory 244516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309536337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3309536337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3803458949
Short name T414
Test name
Test status
Simulation time 302323551 ps
CPU time 1.18 seconds
Started Sep 24 09:39:06 PM UTC 24
Finished Sep 24 09:39:18 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803458949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3803458949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.3219210715
Short name T401
Test name
Test status
Simulation time 186703853 ps
CPU time 0.85 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219210715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3219210715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.4146064764
Short name T418
Test name
Test status
Simulation time 1972705003 ps
CPU time 6.38 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:19 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146064764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4146064764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2534441324
Short name T412
Test name
Test status
Simulation time 99282481 ps
CPU time 0.91 seconds
Started Sep 24 09:39:06 PM UTC 24
Finished Sep 24 09:39:18 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534441324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2534441324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2440295467
Short name T404
Test name
Test status
Simulation time 192458073 ps
CPU time 1.3 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440295467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2440295467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3464673871
Short name T435
Test name
Test status
Simulation time 1618715654 ps
CPU time 7.14 seconds
Started Sep 24 09:39:06 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464673871 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3464673871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2329933011
Short name T405
Test name
Test status
Simulation time 132285056 ps
CPU time 1.59 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:15 PM UTC 24
Peak memory 219424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329933011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2329933011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1757875120
Short name T403
Test name
Test status
Simulation time 158567395 ps
CPU time 1.27 seconds
Started Sep 24 09:39:04 PM UTC 24
Finished Sep 24 09:39:14 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757875120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1757875120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1813285081
Short name T391
Test name
Test status
Simulation time 77905571 ps
CPU time 0.79 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813285081 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1813285081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1231317735
Short name T411
Test name
Test status
Simulation time 1972424857 ps
CPU time 6.48 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:18 PM UTC 24
Peak memory 243724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231317735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1231317735
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2141686691
Short name T392
Test name
Test status
Simulation time 301866453 ps
CPU time 1.09 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141686691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2141686691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.3964044707
Short name T388
Test name
Test status
Simulation time 156291440 ps
CPU time 0.82 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964044707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3964044707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.308727624
Short name T417
Test name
Test status
Simulation time 2250431705 ps
CPU time 7.84 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:19 PM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308727624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.308727624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2779549437
Short name T393
Test name
Test status
Simulation time 177567290 ps
CPU time 1.15 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779549437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2779549437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1408262621
Short name T389
Test name
Test status
Simulation time 118617697 ps
CPU time 1.12 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408262621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1408262621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.2020399319
Short name T394
Test name
Test status
Simulation time 137458005 ps
CPU time 1.06 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020399319 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2020399319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.251092648
Short name T395
Test name
Test status
Simulation time 143861215 ps
CPU time 1.63 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:13 PM UTC 24
Peak memory 219424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251092648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.251092648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.2828397189
Short name T390
Test name
Test status
Simulation time 132648704 ps
CPU time 1.02 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:12 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828397189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2828397189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.513812000
Short name T422
Test name
Test status
Simulation time 63703395 ps
CPU time 0.8 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513812000 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.513812000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1314038994
Short name T439
Test name
Test status
Simulation time 2465767664 ps
CPU time 9.09 seconds
Started Sep 24 09:39:14 PM UTC 24
Finished Sep 24 09:39:25 PM UTC 24
Peak memory 244544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314038994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1314038994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.636975578
Short name T408
Test name
Test status
Simulation time 302745096 ps
CPU time 1.11 seconds
Started Sep 24 09:39:14 PM UTC 24
Finished Sep 24 09:39:17 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636975578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.636975578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.1207118759
Short name T415
Test name
Test status
Simulation time 142325972 ps
CPU time 0.83 seconds
Started Sep 24 09:39:13 PM UTC 24
Finished Sep 24 09:39:18 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207118759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1207118759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.641344190
Short name T421
Test name
Test status
Simulation time 976823892 ps
CPU time 4.71 seconds
Started Sep 24 09:39:13 PM UTC 24
Finished Sep 24 09:39:22 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641344190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.641344190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2915574101
Short name T407
Test name
Test status
Simulation time 148945817 ps
CPU time 1.07 seconds
Started Sep 24 09:39:14 PM UTC 24
Finished Sep 24 09:39:17 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915574101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2915574101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.1982338108
Short name T396
Test name
Test status
Simulation time 227731282 ps
CPU time 1.46 seconds
Started Sep 24 09:39:09 PM UTC 24
Finished Sep 24 09:39:13 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982338108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1982338108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3642507039
Short name T499
Test name
Test status
Simulation time 5438786638 ps
CPU time 19.49 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:41 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642507039 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3642507039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.3452675869
Short name T419
Test name
Test status
Simulation time 354366584 ps
CPU time 2.16 seconds
Started Sep 24 09:39:14 PM UTC 24
Finished Sep 24 09:39:20 PM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452675869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3452675869
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.4133180078
Short name T416
Test name
Test status
Simulation time 113485312 ps
CPU time 0.92 seconds
Started Sep 24 09:39:14 PM UTC 24
Finished Sep 24 09:39:19 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133180078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4133180078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.876907817
Short name T41
Test name
Test status
Simulation time 68909955 ps
CPU time 1.3 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876907817 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.876907817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.4172934183
Short name T59
Test name
Test status
Simulation time 2268678411 ps
CPU time 9.82 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:47 PM UTC 24
Peak memory 243440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172934183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4172934183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3548740998
Short name T42
Test name
Test status
Simulation time 301079140 ps
CPU time 1.37 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548740998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3548740998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.1789063830
Short name T16
Test name
Test status
Simulation time 77786455 ps
CPU time 1.09 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789063830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1789063830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.4244379040
Short name T55
Test name
Test status
Simulation time 819166090 ps
CPU time 4.68 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244379040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4244379040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1024815570
Short name T69
Test name
Test status
Simulation time 8452343367 ps
CPU time 17.42 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 243636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024815570 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1024815570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3639770097
Short name T40
Test name
Test status
Simulation time 104280999 ps
CPU time 1.35 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639770097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3639770097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2932236028
Short name T39
Test name
Test status
Simulation time 114898739 ps
CPU time 1.42 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:37:38 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932236028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2932236028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.456136548
Short name T149
Test name
Test status
Simulation time 12221708610 ps
CPU time 44.59 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:38:22 PM UTC 24
Peak memory 220340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456136548 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.456136548
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.2306242067
Short name T93
Test name
Test status
Simulation time 139397076 ps
CPU time 1.93 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:39 PM UTC 24
Peak memory 219420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306242067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2306242067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.2047528775
Short name T43
Test name
Test status
Simulation time 250159646 ps
CPU time 1.84 seconds
Started Sep 24 09:37:35 PM UTC 24
Finished Sep 24 09:37:39 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047528775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2047528775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.1075325507
Short name T425
Test name
Test status
Simulation time 67247350 ps
CPU time 0.91 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075325507 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1075325507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.1079657875
Short name T465
Test name
Test status
Simulation time 2255051104 ps
CPU time 8.31 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 243792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079657875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1079657875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1339395681
Short name T427
Test name
Test status
Simulation time 301984404 ps
CPU time 1.14 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 239260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339395681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1339395681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.2623255535
Short name T423
Test name
Test status
Simulation time 155778247 ps
CPU time 0.93 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623255535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2623255535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.1001189019
Short name T452
Test name
Test status
Simulation time 1902014237 ps
CPU time 7.29 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:29 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001189019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1001189019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1626852104
Short name T426
Test name
Test status
Simulation time 168822641 ps
CPU time 1.14 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626852104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1626852104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.1184902462
Short name T424
Test name
Test status
Simulation time 117355628 ps
CPU time 1.17 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184902462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1184902462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.4001063186
Short name T513
Test name
Test status
Simulation time 7018124536 ps
CPU time 22.82 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001063186 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4001063186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.4147783721
Short name T432
Test name
Test status
Simulation time 142986218 ps
CPU time 2.08 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147783721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4147783721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2077076649
Short name T429
Test name
Test status
Simulation time 208608229 ps
CPU time 1.31 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077076649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2077076649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.866862399
Short name T433
Test name
Test status
Simulation time 66531116 ps
CPU time 0.83 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866862399 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.866862399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.1041648882
Short name T470
Test name
Test status
Simulation time 2457674624 ps
CPU time 9.18 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:33 PM UTC 24
Peak memory 243836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041648882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1041648882
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2571647243
Short name T436
Test name
Test status
Simulation time 302869269 ps
CPU time 1.15 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571647243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2571647243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3913741570
Short name T428
Test name
Test status
Simulation time 146526978 ps
CPU time 0.86 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913741570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3913741570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.1242267017
Short name T447
Test name
Test status
Simulation time 1532255541 ps
CPU time 5.78 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242267017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1242267017
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.747321518
Short name T434
Test name
Test status
Simulation time 103995606 ps
CPU time 1.01 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747321518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.747321518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.504623581
Short name T431
Test name
Test status
Simulation time 203567893 ps
CPU time 1.34 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:24 PM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504623581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.504623581
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.61242079
Short name T496
Test name
Test status
Simulation time 4415311431 ps
CPU time 14.88 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 220324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61242079 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.61242079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1069905231
Short name T438
Test name
Test status
Simulation time 375909025 ps
CPU time 2.35 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:25 PM UTC 24
Peak memory 220192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069905231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1069905231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.1082216499
Short name T430
Test name
Test status
Simulation time 148787678 ps
CPU time 1.24 seconds
Started Sep 24 09:39:18 PM UTC 24
Finished Sep 24 09:39:23 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082216499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1082216499
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.3976566747
Short name T443
Test name
Test status
Simulation time 70040346 ps
CPU time 0.93 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976566747 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3976566747
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.4188360681
Short name T469
Test name
Test status
Simulation time 1271831563 ps
CPU time 5.65 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:32 PM UTC 24
Peak memory 244408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188360681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4188360681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1677646831
Short name T449
Test name
Test status
Simulation time 301870201 ps
CPU time 1.33 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 239136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677646831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1677646831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1916834153
Short name T441
Test name
Test status
Simulation time 91731116 ps
CPU time 0.9 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:27 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916834153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1916834153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.868103875
Short name T471
Test name
Test status
Simulation time 1492004642 ps
CPU time 6.21 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:33 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868103875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.868103875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2238915312
Short name T445
Test name
Test status
Simulation time 96737412 ps
CPU time 1.15 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238915312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2238915312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.4206400745
Short name T444
Test name
Test status
Simulation time 111075129 ps
CPU time 1.33 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206400745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4206400745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.4159152292
Short name T467
Test name
Test status
Simulation time 878907868 ps
CPU time 3.99 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:31 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159152292 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4159152292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2014218158
Short name T450
Test name
Test status
Simulation time 375745021 ps
CPU time 2.3 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:29 PM UTC 24
Peak memory 220048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014218158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2014218158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.1065270724
Short name T446
Test name
Test status
Simulation time 205791930 ps
CPU time 1.3 seconds
Started Sep 24 09:39:22 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065270724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1065270724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.1602778215
Short name T451
Test name
Test status
Simulation time 64078329 ps
CPU time 0.83 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:29 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602778215 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1602778215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.4227736935
Short name T472
Test name
Test status
Simulation time 1276953762 ps
CPU time 5.67 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:34 PM UTC 24
Peak memory 244016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227736935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4227736935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1678489334
Short name T463
Test name
Test status
Simulation time 301122575 ps
CPU time 1.7 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678489334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1678489334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.738785239
Short name T442
Test name
Test status
Simulation time 91444286 ps
CPU time 0.79 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738785239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.738785239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1843931628
Short name T473
Test name
Test status
Simulation time 1761544828 ps
CPU time 7.08 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:34 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843931628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1843931628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4084401039
Short name T459
Test name
Test status
Simulation time 169192691 ps
CPU time 1.58 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084401039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4084401039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.4294597592
Short name T448
Test name
Test status
Simulation time 114621641 ps
CPU time 1.18 seconds
Started Sep 24 09:39:23 PM UTC 24
Finished Sep 24 09:39:28 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294597592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4294597592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.849761051
Short name T458
Test name
Test status
Simulation time 255662103 ps
CPU time 1.45 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849761051 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.849761051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.3398706856
Short name T464
Test name
Test status
Simulation time 364164129 ps
CPU time 2.1 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398706856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3398706856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.2212327192
Short name T455
Test name
Test status
Simulation time 210858405 ps
CPU time 1.41 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212327192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2212327192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.2168927016
Short name T456
Test name
Test status
Simulation time 87396958 ps
CPU time 0.93 seconds
Started Sep 24 09:39:28 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168927016 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2168927016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.1977558737
Short name T478
Test name
Test status
Simulation time 2242959664 ps
CPU time 7.39 seconds
Started Sep 24 09:39:28 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 244520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977558737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1977558737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1842406920
Short name T461
Test name
Test status
Simulation time 302331817 ps
CPU time 1.2 seconds
Started Sep 24 09:39:28 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842406920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1842406920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.1509905372
Short name T454
Test name
Test status
Simulation time 126028596 ps
CPU time 1.02 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:29 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509905372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1509905372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.1459829043
Short name T468
Test name
Test status
Simulation time 796414411 ps
CPU time 3.64 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:32 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459829043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1459829043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1280229642
Short name T460
Test name
Test status
Simulation time 103115862 ps
CPU time 1.18 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280229642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1280229642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.247045167
Short name T462
Test name
Test status
Simulation time 233484081 ps
CPU time 1.49 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247045167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.247045167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.512057853
Short name T475
Test name
Test status
Simulation time 1528377562 ps
CPU time 6.72 seconds
Started Sep 24 09:39:28 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512057853 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.512057853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1078001012
Short name T466
Test name
Test status
Simulation time 126705783 ps
CPU time 1.79 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:30 PM UTC 24
Peak memory 219440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078001012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1078001012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.489144044
Short name T453
Test name
Test status
Simulation time 82574979 ps
CPU time 0.94 seconds
Started Sep 24 09:39:27 PM UTC 24
Finished Sep 24 09:39:29 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489144044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.489144044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1463673789
Short name T479
Test name
Test status
Simulation time 62022552 ps
CPU time 0.75 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463673789 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1463673789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.409938533
Short name T498
Test name
Test status
Simulation time 1282370904 ps
CPU time 5.78 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:41 PM UTC 24
Peak memory 243668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409938533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.409938533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1745280491
Short name T482
Test name
Test status
Simulation time 303334780 ps
CPU time 1.11 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745280491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1745280491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3220728715
Short name T476
Test name
Test status
Simulation time 85040624 ps
CPU time 0.75 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220728715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3220728715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3386734423
Short name T500
Test name
Test status
Simulation time 1668460901 ps
CPU time 6.66 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:42 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386734423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3386734423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4035671633
Short name T480
Test name
Test status
Simulation time 172029085 ps
CPU time 1.19 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035671633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4035671633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.709336627
Short name T481
Test name
Test status
Simulation time 231362182 ps
CPU time 1.47 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709336627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.709336627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.3429924256
Short name T474
Test name
Test status
Simulation time 11321159710 ps
CPU time 43.96 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:40:20 PM UTC 24
Peak memory 220336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429924256 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3429924256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.83127533
Short name T493
Test name
Test status
Simulation time 406200336 ps
CPU time 2.74 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 220032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83127533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.83127533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.3626952837
Short name T477
Test name
Test status
Simulation time 69939771 ps
CPU time 0.79 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:36 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626952837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3626952837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3466665293
Short name T487
Test name
Test status
Simulation time 70372596 ps
CPU time 0.81 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466665293 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3466665293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.1194092297
Short name T512
Test name
Test status
Simulation time 2431847567 ps
CPU time 8.49 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 244540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194092297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1194092297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.169204800
Short name T489
Test name
Test status
Simulation time 300904095 ps
CPU time 1.22 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169204800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.169204800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2009382323
Short name T484
Test name
Test status
Simulation time 211873139 ps
CPU time 1.02 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009382323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2009382323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2492396867
Short name T502
Test name
Test status
Simulation time 2003551792 ps
CPU time 7.14 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:43 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492396867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2492396867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.231603947
Short name T486
Test name
Test status
Simulation time 141067419 ps
CPU time 1.12 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231603947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.231603947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.1398835842
Short name T488
Test name
Test status
Simulation time 112999767 ps
CPU time 1.29 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398835842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1398835842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.4114048205
Short name T529
Test name
Test status
Simulation time 6166835306 ps
CPU time 29.32 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:40:06 PM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114048205 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4114048205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.2800404280
Short name T490
Test name
Test status
Simulation time 134367495 ps
CPU time 1.66 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 210056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800404280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2800404280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.3416063867
Short name T483
Test name
Test status
Simulation time 113111715 ps
CPU time 0.9 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416063867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3416063867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.3921291372
Short name T505
Test name
Test status
Simulation time 57860438 ps
CPU time 0.76 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:44 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921291372 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3921291372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.186084752
Short name T501
Test name
Test status
Simulation time 1269421840 ps
CPU time 5.32 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:42 PM UTC 24
Peak memory 244020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186084752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.186084752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1491423280
Short name T495
Test name
Test status
Simulation time 302195095 ps
CPU time 1.28 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491423280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1491423280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.68783740
Short name T485
Test name
Test status
Simulation time 101195905 ps
CPU time 0.75 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:37 PM UTC 24
Peak memory 210104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68783740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.68783740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.1769786063
Short name T503
Test name
Test status
Simulation time 1914511416 ps
CPU time 7.07 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:44 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769786063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1769786063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3249689435
Short name T492
Test name
Test status
Simulation time 146154257 ps
CPU time 1.19 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249689435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3249689435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.4110471801
Short name T494
Test name
Test status
Simulation time 194156705 ps
CPU time 1.39 seconds
Started Sep 24 09:39:34 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110471801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4110471801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.4118814108
Short name T530
Test name
Test status
Simulation time 8159963658 ps
CPU time 30.92 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:40:15 PM UTC 24
Peak memory 220532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118814108 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4118814108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.1048701335
Short name T497
Test name
Test status
Simulation time 396871675 ps
CPU time 2.37 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:39 PM UTC 24
Peak memory 211176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048701335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1048701335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.912198872
Short name T491
Test name
Test status
Simulation time 135532717 ps
CPU time 1.22 seconds
Started Sep 24 09:39:35 PM UTC 24
Finished Sep 24 09:39:38 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912198872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.912198872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2748429042
Short name T511
Test name
Test status
Simulation time 67813287 ps
CPU time 0.87 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748429042 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2748429042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.2746970780
Short name T526
Test name
Test status
Simulation time 1951625642 ps
CPU time 7.37 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:51 PM UTC 24
Peak memory 244472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746970780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2746970780
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1578686808
Short name T510
Test name
Test status
Simulation time 302742162 ps
CPU time 1.19 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578686808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1578686808
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.2611159621
Short name T506
Test name
Test status
Simulation time 141198629 ps
CPU time 0.87 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:44 PM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611159621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2611159621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.2782594247
Short name T522
Test name
Test status
Simulation time 1309285284 ps
CPU time 5.07 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:49 PM UTC 24
Peak memory 211076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782594247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2782594247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3957504800
Short name T509
Test name
Test status
Simulation time 170664843 ps
CPU time 1.12 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957504800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3957504800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.768851578
Short name T507
Test name
Test status
Simulation time 108484907 ps
CPU time 1.2 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:44 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768851578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.768851578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.1523651490
Short name T527
Test name
Test status
Simulation time 4328813669 ps
CPU time 19.52 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:40:04 PM UTC 24
Peak memory 220528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523651490 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1523651490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.2618420776
Short name T518
Test name
Test status
Simulation time 348494165 ps
CPU time 2.13 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:46 PM UTC 24
Peak memory 211128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618420776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2618420776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.1953360716
Short name T508
Test name
Test status
Simulation time 133039031 ps
CPU time 0.96 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953360716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1953360716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2845196816
Short name T515
Test name
Test status
Simulation time 67565085 ps
CPU time 1.14 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845196816 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2845196816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3928558992
Short name T525
Test name
Test status
Simulation time 1270532681 ps
CPU time 6.08 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:50 PM UTC 24
Peak memory 244164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928558992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3928558992
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.773907527
Short name T516
Test name
Test status
Simulation time 301857841 ps
CPU time 1.21 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773907527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.773907527
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.492012766
Short name T514
Test name
Test status
Simulation time 192365399 ps
CPU time 1.1 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:45 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492012766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.492012766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.1745092706
Short name T524
Test name
Test status
Simulation time 1232908087 ps
CPU time 5.56 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:50 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745092706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1745092706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3219025199
Short name T519
Test name
Test status
Simulation time 143446936 ps
CPU time 1.5 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:46 PM UTC 24
Peak memory 210076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219025199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3219025199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.4247397391
Short name T520
Test name
Test status
Simulation time 226495111 ps
CPU time 1.73 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:46 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247397391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4247397391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1375376762
Short name T528
Test name
Test status
Simulation time 4134186121 ps
CPU time 20.46 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:40:05 PM UTC 24
Peak memory 220592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375376762 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1375376762
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.283360858
Short name T521
Test name
Test status
Simulation time 291033398 ps
CPU time 1.79 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:46 PM UTC 24
Peak memory 219440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283360858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.283360858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.701730973
Short name T517
Test name
Test status
Simulation time 134240503 ps
CPU time 1.33 seconds
Started Sep 24 09:39:42 PM UTC 24
Finished Sep 24 09:39:46 PM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701730973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.701730973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.77735581
Short name T52
Test name
Test status
Simulation time 52647264 ps
CPU time 1.12 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77735581 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.77735581
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4112883050
Short name T28
Test name
Test status
Simulation time 1967217425 ps
CPU time 7.48 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:46 PM UTC 24
Peak memory 244452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112883050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4112883050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.49558405
Short name T166
Test name
Test status
Simulation time 302524512 ps
CPU time 1.5 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:40 PM UTC 24
Peak memory 239268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49558405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.49558405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.3537417101
Short name T17
Test name
Test status
Simulation time 159790078 ps
CPU time 1.13 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537417101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3537417101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1422124166
Short name T167
Test name
Test status
Simulation time 102415006 ps
CPU time 1.77 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:40 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422124166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1422124166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3518293274
Short name T95
Test name
Test status
Simulation time 266572383 ps
CPU time 2.23 seconds
Started Sep 24 09:37:36 PM UTC 24
Finished Sep 24 09:37:39 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518293274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3518293274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3217540777
Short name T114
Test name
Test status
Simulation time 4170113704 ps
CPU time 21.33 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:38:01 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217540777 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3217540777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1142250414
Short name T94
Test name
Test status
Simulation time 125825642 ps
CPU time 1.93 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:40 PM UTC 24
Peak memory 219436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142250414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1142250414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1166199538
Short name T158
Test name
Test status
Simulation time 78239206 ps
CPU time 1.14 seconds
Started Sep 24 09:37:37 PM UTC 24
Finished Sep 24 09:37:39 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166199538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1166199538
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.4121547449
Short name T58
Test name
Test status
Simulation time 61279605 ps
CPU time 1.06 seconds
Started Sep 24 09:37:40 PM UTC 24
Finished Sep 24 09:37:42 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121547449 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4121547449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.812637243
Short name T44
Test name
Test status
Simulation time 2452374035 ps
CPU time 10.47 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:51 PM UTC 24
Peak memory 244540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812637243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.812637243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.311915991
Short name T168
Test name
Test status
Simulation time 301400617 ps
CPU time 1.9 seconds
Started Sep 24 09:37:40 PM UTC 24
Finished Sep 24 09:37:43 PM UTC 24
Peak memory 239276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311915991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.311915991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1312467506
Short name T18
Test name
Test status
Simulation time 196994506 ps
CPU time 1.43 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312467506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1312467506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.3585783451
Short name T109
Test name
Test status
Simulation time 784777682 ps
CPU time 5.31 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585783451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3585783451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.415202247
Short name T54
Test name
Test status
Simulation time 186114542 ps
CPU time 1.29 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415202247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.415202247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4277812364
Short name T53
Test name
Test status
Simulation time 119915596 ps
CPU time 1.48 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:41 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277812364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4277812364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.3248432967
Short name T146
Test name
Test status
Simulation time 10629565782 ps
CPU time 34.42 seconds
Started Sep 24 09:37:40 PM UTC 24
Finished Sep 24 09:38:16 PM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248432967 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3248432967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.66845164
Short name T57
Test name
Test status
Simulation time 356373996 ps
CPU time 2.36 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:42 PM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66845164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.66845164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3227752610
Short name T56
Test name
Test status
Simulation time 222289501 ps
CPU time 1.75 seconds
Started Sep 24 09:37:39 PM UTC 24
Finished Sep 24 09:37:42 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227752610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3227752610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2593759100
Short name T169
Test name
Test status
Simulation time 71068726 ps
CPU time 0.99 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:44 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593759100 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2593759100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.1385771806
Short name T30
Test name
Test status
Simulation time 2246136772 ps
CPU time 9.18 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:52 PM UTC 24
Peak memory 244612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385771806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1385771806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1789781888
Short name T171
Test name
Test status
Simulation time 301209395 ps
CPU time 1.63 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789781888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1789781888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.649197019
Short name T19
Test name
Test status
Simulation time 151195954 ps
CPU time 1.44 seconds
Started Sep 24 09:37:40 PM UTC 24
Finished Sep 24 09:37:43 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649197019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.649197019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.120041233
Short name T131
Test name
Test status
Simulation time 1377157300 ps
CPU time 5.97 seconds
Started Sep 24 09:37:41 PM UTC 24
Finished Sep 24 09:37:48 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120041233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.120041233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.823369820
Short name T170
Test name
Test status
Simulation time 102324082 ps
CPU time 1.59 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:44 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823369820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.823369820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.1525825333
Short name T97
Test name
Test status
Simulation time 112564179 ps
CPU time 1.5 seconds
Started Sep 24 09:37:40 PM UTC 24
Finished Sep 24 09:37:43 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525825333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1525825333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.1757462003
Short name T337
Test name
Test status
Simulation time 15805871243 ps
CPU time 54.74 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:38:38 PM UTC 24
Peak memory 220480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757462003 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1757462003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1886097980
Short name T7
Test name
Test status
Simulation time 371665786 ps
CPU time 2.81 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:46 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886097980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1886097980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2067144435
Short name T159
Test name
Test status
Simulation time 228024588 ps
CPU time 2.19 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067144435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2067144435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.1080585157
Short name T172
Test name
Test status
Simulation time 69076466 ps
CPU time 1.23 seconds
Started Sep 24 09:37:44 PM UTC 24
Finished Sep 24 09:37:46 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080585157 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1080585157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.440783800
Short name T29
Test name
Test status
Simulation time 1270410630 ps
CPU time 5.94 seconds
Started Sep 24 09:37:43 PM UTC 24
Finished Sep 24 09:37:51 PM UTC 24
Peak memory 244416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440783800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.440783800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2537156895
Short name T174
Test name
Test status
Simulation time 302029491 ps
CPU time 1.75 seconds
Started Sep 24 09:37:44 PM UTC 24
Finished Sep 24 09:37:46 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537156895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2537156895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.579415849
Short name T20
Test name
Test status
Simulation time 223447045 ps
CPU time 1.57 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579415849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.579415849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2155158642
Short name T110
Test name
Test status
Simulation time 947411613 ps
CPU time 6.83 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:50 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155158642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2155158642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3129875456
Short name T173
Test name
Test status
Simulation time 97909489 ps
CPU time 1.54 seconds
Started Sep 24 09:37:43 PM UTC 24
Finished Sep 24 09:37:46 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129875456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3129875456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2718910010
Short name T96
Test name
Test status
Simulation time 190122640 ps
CPU time 1.72 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718910010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2718910010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.3003480250
Short name T111
Test name
Test status
Simulation time 1800202291 ps
CPU time 6.93 seconds
Started Sep 24 09:37:44 PM UTC 24
Finished Sep 24 09:37:52 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003480250 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3003480250
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3848386014
Short name T175
Test name
Test status
Simulation time 370539008 ps
CPU time 2.71 seconds
Started Sep 24 09:37:43 PM UTC 24
Finished Sep 24 09:37:47 PM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848386014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3848386014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3851024559
Short name T165
Test name
Test status
Simulation time 159289620 ps
CPU time 1.67 seconds
Started Sep 24 09:37:42 PM UTC 24
Finished Sep 24 09:37:45 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851024559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3851024559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2337200148
Short name T176
Test name
Test status
Simulation time 80440292 ps
CPU time 1.03 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:48 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337200148 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2337200148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.1995152697
Short name T31
Test name
Test status
Simulation time 1959054432 ps
CPU time 7.32 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:55 PM UTC 24
Peak memory 244220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995152697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1995152697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1880088950
Short name T179
Test name
Test status
Simulation time 301162455 ps
CPU time 1.56 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 239272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880088950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1880088950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3071213013
Short name T21
Test name
Test status
Simulation time 140026300 ps
CPU time 1.1 seconds
Started Sep 24 09:37:45 PM UTC 24
Finished Sep 24 09:37:47 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071213013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3071213013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3427424520
Short name T119
Test name
Test status
Simulation time 1703453755 ps
CPU time 6.99 seconds
Started Sep 24 09:37:45 PM UTC 24
Finished Sep 24 09:37:53 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427424520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3427424520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1962217845
Short name T178
Test name
Test status
Simulation time 103449605 ps
CPU time 1.52 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962217845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1962217845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2104846483
Short name T160
Test name
Test status
Simulation time 230998266 ps
CPU time 2.17 seconds
Started Sep 24 09:37:45 PM UTC 24
Finished Sep 24 09:37:48 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104846483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2104846483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1211524366
Short name T180
Test name
Test status
Simulation time 195247910 ps
CPU time 1.68 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211524366 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1211524366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2345637984
Short name T181
Test name
Test status
Simulation time 368209686 ps
CPU time 2.29 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:50 PM UTC 24
Peak memory 211080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345637984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2345637984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.4274880416
Short name T164
Test name
Test status
Simulation time 146527979 ps
CPU time 1.47 seconds
Started Sep 24 09:37:46 PM UTC 24
Finished Sep 24 09:37:49 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274880416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.4274880416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest
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