Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	599946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

359251

1

T1

136

T3

132

T4

874

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	511199	1			T1	186		T2	1		T3	168
values[0x0]	223897	1			T1	103		T3	89		T4	488
values[0x1]	224101	1			T1	90		T3	92		T4	512

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	503707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

455490

1

T1

166

T3

162

T4

1104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4835	1			T5	4		T11	3		T12	3
valid_sources[0x01]	4424	1			T5	2		T6	1		T11	3
valid_sources[0x02]	3269	1			T2	1		T5	4		T11	2
valid_sources[0x03]	3462	1			T5	6		T6	3		T11	3
valid_sources[0x04]	3474	1			T1	9		T5	5		T11	2
valid_sources[0x05]	3800	1			T1	23		T5	3		T10	5
valid_sources[0x06]	3566	1			T5	3		T6	8		T11	2
valid_sources[0x07]	3971	1			T5	6		T6	1		T12	3
valid_sources[0x08]	3030	1			T5	5		T12	2		T22	22
valid_sources[0x09]	3879	1			T5	4		T6	2		T12	4
valid_sources[0x0a]	3446	1			T5	6		T10	1		T11	1
valid_sources[0x0b]	3810	1			T5	1		T11	3		T12	3
valid_sources[0x0c]	3763	1			T5	2		T6	1		T11	1
valid_sources[0x0d]	3702	1			T5	3		T11	1		T12	5
valid_sources[0x0e]	3658	1			T4	6		T5	1		T6	1
valid_sources[0x0f]	3143	1			T5	4		T12	5		T22	17
valid_sources[0x10]	4162	1			T1	14		T5	3		T6	1
valid_sources[0x11]	2965	1			T5	1		T6	1		T11	4
valid_sources[0x12]	4106	1			T5	2		T6	1		T11	1
valid_sources[0x13]	3724	1			T5	3		T11	3		T12	3
valid_sources[0x14]	3322	1			T1	18		T5	6		T11	3
valid_sources[0x15]	3171	1			T5	3		T11	1		T12	3
valid_sources[0x16]	4108	1			T5	5		T6	2		T12	1
valid_sources[0x17]	4159	1			T5	5		T11	2		T12	3
valid_sources[0x18]	4270	1			T5	3		T11	3		T12	3
valid_sources[0x19]	3730	1			T4	8		T5	5		T6	1
valid_sources[0x1a]	3547	1			T5	6		T6	1		T9	1
valid_sources[0x1b]	3362	1			T5	7		T10	1		T12	6
valid_sources[0x1c]	3517	1			T5	2		T12	1		T50	7
valid_sources[0x1d]	3340	1			T5	4		T6	1		T11	2
valid_sources[0x1e]	3976	1			T5	4		T6	3		T12	3
valid_sources[0x1f]	3255	1			T5	5		T6	3		T11	1
valid_sources[0x20]	3037	1			T5	3		T11	3		T12	2
valid_sources[0x21]	4405	1			T5	6		T12	3		T22	8
valid_sources[0x22]	4234	1			T5	1		T12	4		T22	9
valid_sources[0x23]	3222	1			T5	3		T8	1		T11	3
valid_sources[0x24]	3234	1			T5	2		T6	3		T10	6
valid_sources[0x25]	3454	1			T5	2		T6	1		T12	3
valid_sources[0x26]	3255	1			T5	7		T12	3		T22	13
valid_sources[0x27]	4560	1			T1	6		T5	2		T11	2
valid_sources[0x28]	3606	1			T5	4		T11	3		T12	1
valid_sources[0x29]	2898	1			T5	5		T6	1		T11	1
valid_sources[0x2a]	3570	1			T5	3		T12	4		T22	13
valid_sources[0x2b]	3408	1			T5	3		T11	3		T12	4
valid_sources[0x2c]	4006	1			T5	2		T8	1		T11	2
valid_sources[0x2d]	3786	1			T5	4		T11	1		T12	1
valid_sources[0x2e]	3090	1			T5	2		T22	12		T62	1
valid_sources[0x2f]	3971	1			T5	6		T11	1		T12	5
valid_sources[0x30]	4698	1			T5	2		T11	1		T12	2
valid_sources[0x31]	3225	1			T5	5		T12	5		T22	10
valid_sources[0x32]	5219	1			T11	1		T12	4		T22	2
valid_sources[0x33]	3989	1			T5	5		T6	2		T11	3
valid_sources[0x34]	3156	1			T1	8		T5	4		T11	5
valid_sources[0x35]	3657	1			T5	5		T12	5		T22	18
valid_sources[0x36]	3379	1			T5	1		T11	1		T22	16
valid_sources[0x37]	3444	1			T1	12		T5	6		T6	2
valid_sources[0x38]	4682	1			T1	8		T5	5		T12	6
valid_sources[0x39]	4458	1			T5	3		T8	1		T11	1
valid_sources[0x3a]	3011	1			T5	2		T11	1		T12	2
valid_sources[0x3b]	3808	1			T5	1		T11	2		T12	2
valid_sources[0x3c]	3416	1			T5	2		T6	1		T11	2
valid_sources[0x3d]	3463	1			T5	5		T12	4		T22	13
valid_sources[0x3e]	3202	1			T5	4		T12	3		T22	10
valid_sources[0x3f]	3326	1			T5	3		T6	2		T12	1
valid_sources[0x40]	3548	1			T5	2		T6	5		T11	2
valid_sources[0x41]	3487	1			T4	156		T5	5		T11	5
valid_sources[0x42]	4122	1			T5	6		T22	22		T23	37
valid_sources[0x43]	3782	1			T5	3		T6	2		T11	1
valid_sources[0x44]	4411	1			T5	2		T11	1		T12	3
valid_sources[0x45]	3055	1			T5	5		T12	7		T22	12
valid_sources[0x46]	3778	1			T5	4		T10	13		T11	2
valid_sources[0x47]	4034	1			T5	4		T11	3		T12	2
valid_sources[0x48]	3773	1			T1	42		T4	113		T5	6
valid_sources[0x49]	3700	1			T4	1		T5	3		T10	11
valid_sources[0x4a]	3498	1			T5	6		T6	1		T10	7
valid_sources[0x4b]	3846	1			T4	155		T5	6		T6	4
valid_sources[0x4c]	7021	1			T5	6		T6	1		T12	2
valid_sources[0x4d]	4310	1			T5	6		T11	2		T12	3
valid_sources[0x4e]	3216	1			T5	1		T11	1		T12	6
valid_sources[0x4f]	3566	1			T5	2		T6	2		T8	2
valid_sources[0x50]	3754	1			T5	6		T6	1		T10	7
valid_sources[0x51]	3750	1			T5	5		T10	2		T12	2
valid_sources[0x52]	3197	1			T5	6		T6	1		T11	4
valid_sources[0x53]	3342	1			T5	4		T10	7		T11	3
valid_sources[0x54]	3857	1			T5	6		T11	5		T12	6
valid_sources[0x55]	3303	1			T4	188		T5	4		T10	2
valid_sources[0x56]	3756	1			T5	1		T11	1		T12	2
valid_sources[0x57]	3201	1			T5	3		T11	1		T12	2
valid_sources[0x58]	6675	1			T5	8		T10	7		T11	2
valid_sources[0x59]	3244	1			T5	3		T6	4		T11	3
valid_sources[0x5a]	3764	1			T4	126		T5	5		T6	3
valid_sources[0x5b]	3918	1			T5	5		T6	1		T12	7
valid_sources[0x5c]	3282	1			T5	5		T6	2		T11	2
valid_sources[0x5d]	3569	1			T5	2		T6	1		T11	1
valid_sources[0x5e]	4208	1			T5	2		T11	1		T12	4
valid_sources[0x5f]	3219	1			T5	1		T8	1		T12	1
valid_sources[0x60]	3554	1			T5	5		T6	2		T11	3
valid_sources[0x61]	3505	1			T5	4		T11	2		T12	6
valid_sources[0x62]	3273	1			T5	4		T12	3		T22	19
valid_sources[0x63]	7421	1			T1	10		T5	4		T6	1
valid_sources[0x64]	3532	1			T5	5		T6	1		T11	5
valid_sources[0x65]	3353	1			T5	2		T6	1		T10	8
valid_sources[0x66]	3803	1			T5	5		T10	4		T12	1
valid_sources[0x67]	3288	1			T5	3		T11	4		T12	4
valid_sources[0x68]	3596	1			T5	5		T11	3		T12	2
valid_sources[0x69]	5229	1			T5	6		T11	1		T12	2
valid_sources[0x6a]	2971	1			T5	6		T6	1		T11	5
valid_sources[0x6b]	5142	1			T5	7		T10	5		T12	5
valid_sources[0x6c]	2752	1			T5	1		T6	1		T11	2
valid_sources[0x6d]	3346	1			T5	3		T6	1		T22	11
valid_sources[0x6e]	4262	1			T5	1		T11	3		T12	2
valid_sources[0x6f]	3348	1			T5	2		T6	2		T11	1
valid_sources[0x70]	3112	1			T4	1		T5	4		T12	4
valid_sources[0x71]	3451	1			T5	2		T6	2		T11	1
valid_sources[0x72]	3185	1			T5	6		T11	4		T12	1
valid_sources[0x73]	3331	1			T5	4		T6	1		T11	1
valid_sources[0x74]	3495	1			T5	2		T6	2		T12	2
valid_sources[0x75]	3523	1			T4	112		T5	8		T6	2
valid_sources[0x76]	3091	1			T5	5		T11	3		T12	1
valid_sources[0x77]	3593	1			T5	6		T6	1		T11	6
valid_sources[0x78]	3424	1			T5	5		T6	2		T8	1
valid_sources[0x79]	3369	1			T5	6		T11	1		T12	1
valid_sources[0x7a]	3678	1			T4	367		T11	2		T12	3
valid_sources[0x7b]	3287	1			T5	7		T12	2		T22	12
valid_sources[0x7c]	3959	1			T5	3		T11	3		T12	5
valid_sources[0x7d]	4217	1			T1	11		T5	3		T11	1
valid_sources[0x7e]	2987	1			T5	3		T6	2		T11	6
valid_sources[0x7f]	7851	1			T5	4		T12	1		T22	22
valid_sources[0x80]	3653	1			T5	6		T6	1		T12	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

239463

1

T1

83

T3

95

T4

643

values[0x0]

all_enables

biggest_size

78174

1

T1

34

T3

20

T4

154

values[0x1]

all_enables

biggest_size

41614

1

T1

19

T3

17

T4

77