Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11182148	12761	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11182148	117651	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11182148	6521481	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11182148	187922	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11182148	12761	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11182148	117651	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11182148	6521481	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11182148	187922	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	12761	0	0
T1	2644	4	0	0
T2	1917	0	0	0
T3	2680	17	0	0
T4	30231	28	0	0
T5	8799	0	0	0
T6	4132	4	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	10	0	0
T11	0	4	0	0
T13	0	4	0	0
T22	0	36	0	0
T23	0	78	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	117651	0	0
T1	2644	38	0	0
T2	1917	0	0	0
T3	2680	153	0	0
T4	30231	259	0	0
T5	8799	0	0	0
T6	4132	38	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	90	0	0
T11	0	37	0	0
T13	0	38	0	0
T22	0	332	0	0
T23	0	739	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	6521481	0	0
T1	2644	1667	0	0
T2	1917	689	0	0
T3	2680	1846	0	0
T4	30231	22264	0	0
T5	8799	8208	0	0
T6	4132	3145	0	0
T7	6804	675	0	0
T8	1483	913	0	0
T9	4068	653	0	0
T10	3802	3026	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	187922	0	0
T1	2644	63	0	0
T2	1917	0	0	0
T3	2680	255	0	0
T4	30231	418	0	0
T5	8799	0	0	0
T6	4132	65	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	127	0	0
T11	0	70	0	0
T13	0	55	0	0
T22	0	522	0	0
T23	0	1196	0	0
T24	0	72	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	12761	0	0
T1	2644	4	0	0
T2	1917	0	0	0
T3	2680	17	0	0
T4	30231	28	0	0
T5	8799	0	0	0
T6	4132	4	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	10	0	0
T11	0	4	0	0
T13	0	4	0	0
T22	0	36	0	0
T23	0	78	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	117651	0	0
T1	2644	38	0	0
T2	1917	0	0	0
T3	2680	153	0	0
T4	30231	259	0	0
T5	8799	0	0	0
T6	4132	38	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	90	0	0
T11	0	37	0	0
T13	0	38	0	0
T22	0	332	0	0
T23	0	739	0	0
T24	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	6521481	0	0
T1	2644	1667	0	0
T2	1917	689	0	0
T3	2680	1846	0	0
T4	30231	22264	0	0
T5	8799	8208	0	0
T6	4132	3145	0	0
T7	6804	675	0	0
T8	1483	913	0	0
T9	4068	653	0	0
T10	3802	3026	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11182148	187922	0	0
T1	2644	63	0	0
T2	1917	0	0	0
T3	2680	255	0	0
T4	30231	418	0	0
T5	8799	0	0	0
T6	4132	65	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	127	0	0
T11	0	70	0	0
T13	0	55	0	0
T22	0	522	0	0
T23	0	1196	0	0
T24	0	72	0	0