Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T50
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T50
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T50
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12601978	13646	0	0
gen_assertions[0].RstEnOn_A	12601978	1043	0	0
gen_assertions[0].RstNOff_A	12601978	13646	0	0
gen_assertions[0].RstNOn_A	12601978	1043	0	0
gen_assertions[1].RstEnOff_A	50408579	12386	0	0
gen_assertions[1].RstEnOn_A	50408579	992	0	0
gen_assertions[1].RstNOff_A	50408579	12386	0	0
gen_assertions[1].RstNOn_A	50408579	992	0	0
gen_assertions[2].RstEnOff_A	25205250	12434	0	0
gen_assertions[2].RstEnOn_A	25205250	992	0	0
gen_assertions[2].RstNOff_A	25205250	12434	0	0
gen_assertions[2].RstNOn_A	25205250	992	0	0
gen_assertions[3].RstEnOff_A	25205103	12513	0	0
gen_assertions[3].RstEnOn_A	25205103	1075	0	0
gen_assertions[3].RstNOff_A	25205103	12513	0	0
gen_assertions[3].RstNOn_A	25205103	1075	0	0
gen_assertions[4].RstEnOff_A	1591058	21019	0	0
gen_assertions[4].RstEnOn_A	1591058	1086	0	0
gen_assertions[4].RstNOff_A	1591058	21019	0	0
gen_assertions[4].RstNOn_A	1591058	1086	0	0
gen_assertions[5].RstEnOff_A	12601978	13881	0	0
gen_assertions[5].RstEnOn_A	12601978	1153	0	0
gen_assertions[5].RstNOff_A	12601978	13881	0	0
gen_assertions[5].RstNOn_A	12601978	1153	0	0
gen_assertions[6].RstEnOff_A	12601978	13935	0	0
gen_assertions[6].RstEnOn_A	12601978	1215	0	0
gen_assertions[6].RstNOff_A	12601978	13935	0	0
gen_assertions[6].RstNOn_A	12601978	1215	0	0
gen_assertions[7].RstEnOff_A	12601978	13984	0	0
gen_assertions[7].RstEnOn_A	12601978	1258	0	0
gen_assertions[7].RstNOff_A	12601978	13984	0	0
gen_assertions[7].RstNOn_A	12601978	1258	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13646	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	7	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1043	0	0
T3	3617	10	0	0
T4	34342	0	0	0
T5	8866	7	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	1	0	0
T11	5307	0	0	0
T12	3166	2	0	0
T24	0	1	0	0
T38	0	6	0	0
T50	0	7	0	0
T55	0	3	0	0
T62	0	5	0	0
T82	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13646	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	7	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1043	0	0
T3	3617	10	0	0
T4	34342	0	0	0
T5	8866	7	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	1	0	0
T11	5307	0	0	0
T12	3166	2	0	0
T24	0	1	0	0
T38	0	6	0	0
T50	0	7	0	0
T55	0	3	0	0
T62	0	5	0	0
T82	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50408579	12386	0	0
T1	11739	4	0	0
T2	8129	0	0	0
T3	14473	17	0	0
T4	137357	25	0	0
T5	35466	10	0	0
T6	17502	4	0	0
T7	28995	0	0	0
T8	6299	0	0	0
T9	16638	0	0	0
T10	17899	9	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50408579	992	0	0
T3	14473	5	0	0
T4	137357	0	0	0
T5	35466	10	0	0
T6	17502	0	0	0
T7	28995	0	0	0
T8	6299	0	0	0
T9	16638	0	0	0
T10	17899	0	0	0
T11	21229	0	0	0
T12	12669	3	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	7	0	0
T51	0	2	0	0
T62	0	8	0	0
T82	0	9	0	0
T83	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50408579	12386	0	0
T1	11739	4	0	0
T2	8129	0	0	0
T3	14473	17	0	0
T4	137357	25	0	0
T5	35466	10	0	0
T6	17502	4	0	0
T7	28995	0	0	0
T8	6299	0	0	0
T9	16638	0	0	0
T10	17899	9	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50408579	992	0	0
T3	14473	5	0	0
T4	137357	0	0	0
T5	35466	10	0	0
T6	17502	0	0	0
T7	28995	0	0	0
T8	6299	0	0	0
T9	16638	0	0	0
T10	17899	0	0	0
T11	21229	0	0	0
T12	12669	3	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	7	0	0
T51	0	2	0	0
T62	0	8	0	0
T82	0	9	0	0
T83	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205250	12434	0	0
T1	5870	5	0	0
T2	4064	0	0	0
T3	7236	17	0	0
T4	68683	25	0	0
T5	17733	7	0	0
T6	8747	4	0	0
T7	14498	0	0	0
T8	3149	0	0	0
T9	8319	0	0	0
T10	8949	9	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205250	992	0	0
T1	5870	1	0	0
T2	4064	0	0	0
T3	7236	1	0	0
T4	68683	0	0	0
T5	17733	7	0	0
T6	8747	0	0	0
T7	14498	0	0	0
T8	3149	0	0	0
T9	8319	0	0	0
T10	8949	0	0	0
T12	0	4	0	0
T24	0	1	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	7	0	0
T51	0	1	0	0
T82	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205250	12434	0	0
T1	5870	5	0	0
T2	4064	0	0	0
T3	7236	17	0	0
T4	68683	25	0	0
T5	17733	7	0	0
T6	8747	4	0	0
T7	14498	0	0	0
T8	3149	0	0	0
T9	8319	0	0	0
T10	8949	9	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205250	992	0	0
T1	5870	1	0	0
T2	4064	0	0	0
T3	7236	1	0	0
T4	68683	0	0	0
T5	17733	7	0	0
T6	8747	0	0	0
T7	14498	0	0	0
T8	3149	0	0	0
T9	8319	0	0	0
T10	8949	0	0	0
T12	0	4	0	0
T24	0	1	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	7	0	0
T51	0	1	0	0
T82	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205103	12513	0	0
T1	5868	5	0	0
T2	4064	0	0	0
T3	7236	17	0	0
T4	68689	25	0	0
T5	17733	8	0	0
T6	8748	4	0	0
T7	14495	0	0	0
T8	3150	0	0	0
T9	8319	0	0	0
T10	8949	9	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205103	1075	0	0
T1	5868	1	0	0
T2	4064	0	0	0
T3	7236	0	0	0
T4	68689	0	0	0
T5	17733	8	0	0
T6	8748	0	0	0
T7	14495	0	0	0
T8	3150	0	0	0
T9	8319	0	0	0
T10	8949	0	0	0
T12	0	4	0	0
T24	0	1	0	0
T38	0	9	0	0
T43	0	10	0	0
T50	0	8	0	0
T51	0	2	0	0
T82	0	11	0	0
T83	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205103	12513	0	0
T1	5868	5	0	0
T2	4064	0	0	0
T3	7236	17	0	0
T4	68689	25	0	0
T5	17733	8	0	0
T6	8748	4	0	0
T7	14495	0	0	0
T8	3150	0	0	0
T9	8319	0	0	0
T10	8949	9	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	31	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25205103	1075	0	0
T1	5868	1	0	0
T2	4064	0	0	0
T3	7236	0	0	0
T4	68689	0	0	0
T5	17733	8	0	0
T6	8748	0	0	0
T7	14495	0	0	0
T8	3150	0	0	0
T9	8319	0	0	0
T10	8949	0	0	0
T12	0	4	0	0
T24	0	1	0	0
T38	0	9	0	0
T43	0	10	0	0
T50	0	8	0	0
T51	0	2	0	0
T82	0	11	0	0
T83	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591058	21019	0	0
T1	367	6	0	0
T2	253	2	0	0
T3	450	17	0	0
T4	4353	45	0	0
T5	1108	12	0	0
T6	545	6	0	0
T7	908	3	0	0
T8	196	1	0	0
T9	518	2	0	0
T10	557	11	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591058	1086	0	0
T5	1108	11	0	0
T6	545	0	0	0
T7	908	0	0	0
T8	196	0	0	0
T9	518	0	0	0
T10	557	0	0	0
T11	663	0	0	0
T12	395	5	0	0
T13	533	0	0	0
T25	902	0	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	8	0	0
T51	0	1	0	0
T82	0	12	0	0
T83	0	7	0	0
T84	0	4	0	0
T85	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591058	21019	0	0
T1	367	6	0	0
T2	253	2	0	0
T3	450	17	0	0
T4	4353	45	0	0
T5	1108	12	0	0
T6	545	6	0	0
T7	908	3	0	0
T8	196	1	0	0
T9	518	2	0	0
T10	557	11	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591058	1086	0	0
T5	1108	11	0	0
T6	545	0	0	0
T7	908	0	0	0
T8	196	0	0	0
T9	518	0	0	0
T10	557	0	0	0
T11	663	0	0	0
T12	395	5	0	0
T13	533	0	0	0
T25	902	0	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	8	0	0
T51	0	1	0	0
T82	0	12	0	0
T83	0	7	0	0
T84	0	4	0	0
T85	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13881	0	0
T1	2935	5	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	14	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1153	0	0
T1	2935	1	0	0
T2	2030	0	0	0
T3	3617	0	0	0
T4	34342	0	0	0
T5	8866	14	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T12	0	7	0	0
T38	0	6	0	0
T43	0	8	0	0
T50	0	11	0	0
T51	0	1	0	0
T82	0	13	0	0
T83	0	7	0	0
T84	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13881	0	0
T1	2935	5	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	14	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1153	0	0
T1	2935	1	0	0
T2	2030	0	0	0
T3	3617	0	0	0
T4	34342	0	0	0
T5	8866	14	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T12	0	7	0	0
T38	0	6	0	0
T43	0	8	0	0
T50	0	11	0	0
T51	0	1	0	0
T82	0	13	0	0
T83	0	7	0	0
T84	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13935	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	9	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1215	0	0
T5	8866	9	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T11	5307	0	0	0
T12	3166	7	0	0
T13	4265	0	0	0
T25	7203	0	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	12	0	0
T51	0	2	0	0
T82	0	14	0	0
T83	0	9	0	0
T84	0	7	0	0
T86	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13935	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	9	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1215	0	0
T5	8866	9	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T11	5307	0	0	0
T12	3166	7	0	0
T13	4265	0	0	0
T25	7203	0	0	0
T38	0	8	0	0
T43	0	10	0	0
T50	0	12	0	0
T51	0	2	0	0
T82	0	14	0	0
T83	0	9	0	0
T84	0	7	0	0
T86	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13984	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	13	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	9	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1258	0	0
T5	8866	13	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T11	5307	0	0	0
T12	3166	9	0	0
T13	4265	0	0	0
T25	7203	0	0	0
T38	0	7	0	0
T43	0	14	0	0
T50	0	13	0	0
T51	0	1	0	0
T82	0	14	0	0
T83	0	8	0	0
T84	0	7	0	0
T85	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	13984	0	0
T1	2935	4	0	0
T2	2030	0	0	0
T3	3617	17	0	0
T4	34342	28	0	0
T5	8866	13	0	0
T6	4374	4	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	10	0	0
T11	0	4	0	0
T12	0	9	0	0
T13	0	4	0	0
T22	0	36	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12601978	1258	0	0
T5	8866	13	0	0
T6	4374	0	0	0
T7	7244	0	0	0
T8	1574	0	0	0
T9	4158	0	0	0
T10	4474	0	0	0
T11	5307	0	0	0
T12	3166	9	0	0
T13	4265	0	0	0
T25	7203	0	0	0
T38	0	7	0	0
T43	0	14	0	0
T50	0	13	0	0
T51	0	1	0	0
T82	0	14	0	0
T83	0	8	0	0
T84	0	7	0	0
T85	0	13	0	0