Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12033793	7424	0	0
alert_regwen_rd_A	12033793	4612	0	0
cpu_regwen_rd_A	12033793	4640	0	0
sw_rst_ctrl_n_0_rd_A	12033793	7807	0	0
sw_rst_ctrl_n_1_rd_A	12033793	7926	0	0
sw_rst_ctrl_n_2_rd_A	12033793	7778	0	0
sw_rst_ctrl_n_3_rd_A	12033793	7784	0	0
sw_rst_ctrl_n_4_rd_A	12033793	8155	0	0
sw_rst_ctrl_n_5_rd_A	12033793	8107	0	0
sw_rst_ctrl_n_6_rd_A	12033793	8048	0	0
sw_rst_ctrl_n_7_rd_A	12033793	8015	0	0
sw_rst_regwen_0_rd_A	12033793	5062	0	0
sw_rst_regwen_1_rd_A	12033793	5073	0	0
sw_rst_regwen_2_rd_A	12033793	5115	0	0
sw_rst_regwen_3_rd_A	12033793	5008	0	0
sw_rst_regwen_4_rd_A	12033793	5140	0	0
sw_rst_regwen_5_rd_A	12033793	4962	0	0
sw_rst_regwen_6_rd_A	12033793	5192	0	0
sw_rst_regwen_7_rd_A	12033793	5049	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	7424	0	0
T72	6275	171	0	0
T73	3183	10	0	0
T74	5856	210	0	0
T75	16667	1	0	0
T76	17315	3	0	0
T77	4029	300	0	0
T78	4724	41	0	0
T87	2145	9	0	0
T88	20857	4	0	0
T89	3026	18	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	4612	0	0
T4	30231	30	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	0	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T94	0	36	0	0
T95	0	42	0	0
T97	0	47	0	0
T98	0	43	0	0
T99	0	76	0	0
T101	0	68	0	0
T112	0	69	0	0
T130	0	11	0	0
T131	0	22	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	4640	0	0
T4	30231	13	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	0	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T94	0	66	0	0
T95	0	25	0	0
T97	0	30	0	0
T98	0	65	0	0
T99	0	77	0	0
T101	0	85	0	0
T112	0	47	0	0
T130	0	18	0	0
T131	0	60	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	7807	0	0
T4	30231	22	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	43	0	0
T11	5017	7	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	19	0	0
T84	0	109	0	0
T94	0	59	0	0
T95	0	40	0	0
T97	0	56	0	0
T98	0	46	0	0
T104	0	10	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	7926	0	0
T4	30231	27	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	36	0	0
T11	5017	3	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	17	0	0
T84	0	130	0	0
T94	0	60	0	0
T95	0	29	0	0
T97	0	37	0	0
T104	0	5	0	0
T132	0	4	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	7778	0	0
T4	30231	23	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	36	0	0
T11	5017	10	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	19	0	0
T84	0	116	0	0
T94	0	82	0	0
T95	0	23	0	0
T97	0	35	0	0
T104	0	7	0	0
T132	0	5	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	7784	0	0
T4	30231	24	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	34	0	0
T11	5017	17	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	26	0	0
T84	0	127	0	0
T94	0	49	0	0
T95	0	39	0	0
T97	0	51	0	0
T98	0	47	0	0
T104	0	3	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	8155	0	0
T4	30231	40	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	26	0	0
T11	5017	12	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	8	0	0
T84	0	134	0	0
T94	0	50	0	0
T95	0	54	0	0
T97	0	47	0	0
T104	0	5	0	0
T132	0	7	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	8107	0	0
T4	30231	18	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	26	0	0
T11	5017	1	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	35	0	0
T84	0	107	0	0
T94	0	50	0	0
T95	0	29	0	0
T97	0	50	0	0
T98	0	55	0	0
T132	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	8048	0	0
T4	30231	9	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	30	0	0
T11	5017	2	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	12	0	0
T84	0	121	0	0
T94	0	59	0	0
T95	0	47	0	0
T97	0	45	0	0
T98	0	56	0	0
T132	0	5	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	8015	0	0
T4	30231	18	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	42	0	0
T11	5017	7	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T55	0	32	0	0
T84	0	124	0	0
T94	0	88	0	0
T95	0	15	0	0
T97	0	53	0	0
T98	0	61	0	0
T99	0	88	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5062	0	0
T4	30231	19	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	3	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	33	0	0
T94	0	60	0	0
T95	0	40	0	0
T97	0	58	0	0
T98	0	24	0	0
T99	0	110	0	0
T101	0	74	0	0
T130	0	28	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5073	0	0
T4	30231	50	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	9	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	32	0	0
T94	0	52	0	0
T95	0	20	0	0
T97	0	43	0	0
T98	0	65	0	0
T99	0	94	0	0
T101	0	64	0	0
T130	0	19	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5115	0	0
T4	30231	64	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	0	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	32	0	0
T94	0	72	0	0
T95	0	11	0	0
T97	0	52	0	0
T98	0	65	0	0
T99	0	96	0	0
T101	0	75	0	0
T130	0	18	0	0
T133	0	24	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5008	0	0
T4	30231	40	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	4	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	34	0	0
T94	0	61	0	0
T95	0	27	0	0
T97	0	35	0	0
T98	0	59	0	0
T99	0	83	0	0
T101	0	71	0	0
T130	0	37	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5140	0	0
T4	30231	34	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	6	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	39	0	0
T94	0	61	0	0
T95	0	28	0	0
T97	0	50	0	0
T98	0	66	0	0
T99	0	63	0	0
T101	0	64	0	0
T130	0	26	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	4962	0	0
T4	30231	24	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	3	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	51	0	0
T94	0	72	0	0
T95	0	27	0	0
T97	0	60	0	0
T98	0	54	0	0
T99	0	97	0	0
T101	0	60	0	0
T130	0	32	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5192	0	0
T4	30231	28	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	3	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	45	0	0
T94	0	57	0	0
T95	0	47	0	0
T97	0	43	0	0
T98	0	45	0	0
T99	0	63	0	0
T101	0	78	0	0
T130	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12033793	5049	0	0
T4	30231	42	0	0
T5	8799	0	0	0
T6	4132	0	0	0
T7	6804	0	0	0
T8	1483	0	0	0
T9	4068	0	0	0
T10	3802	0	0	0
T11	5017	2	0	0
T12	3100	0	0	0
T13	4024	0	0	0
T84	0	34	0	0
T94	0	79	0	0
T95	0	31	0	0
T97	0	70	0	0
T98	0	48	0	0
T99	0	114	0	0
T101	0	61	0	0
T130	0	30	0	0