Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	550875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

331174

1

T2

152

T3

40

T4

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	469353	1			T1	1		T2	186		T3	64
values[0x0]	206515	1			T2	107		T3	26		T4	47
values[0x1]	206181	1			T2	86		T3	41		T4	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	462326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

419723

1

T2

177

T3

51

T4

83

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2838	1			T7	6		T10	3		T12	4
valid_sources[0x01]	3802	1			T7	9		T10	3		T12	1
valid_sources[0x02]	3361	1			T6	27		T7	8		T11	2
valid_sources[0x03]	2515	1			T3	1		T6	4		T7	8
valid_sources[0x04]	5072	1			T6	15		T7	10		T10	1
valid_sources[0x05]	2678	1			T7	7		T10	1		T12	1
valid_sources[0x06]	4083	1			T7	8		T10	2		T12	3
valid_sources[0x07]	2841	1			T7	11		T10	3		T12	3
valid_sources[0x08]	3241	1			T7	9		T10	4		T60	4
valid_sources[0x09]	2750	1			T6	1		T7	14		T10	3
valid_sources[0x0a]	2891	1			T7	11		T10	4		T11	2
valid_sources[0x0b]	4566	1			T3	1		T7	9		T10	1
valid_sources[0x0c]	3474	1			T3	2		T7	9		T10	4
valid_sources[0x0d]	2537	1			T7	7		T10	1		T60	3
valid_sources[0x0e]	3507	1			T6	4		T7	13		T10	3
valid_sources[0x0f]	3269	1			T3	2		T7	8		T12	1
valid_sources[0x10]	3079	1			T7	5		T11	1		T12	2
valid_sources[0x11]	6000	1			T3	1		T7	9		T60	7
valid_sources[0x12]	6024	1			T7	9		T10	6		T60	6
valid_sources[0x13]	2763	1			T7	10		T12	2		T21	3
valid_sources[0x14]	2680	1			T7	8		T11	1		T12	1
valid_sources[0x15]	4070	1			T6	20		T7	9		T10	1
valid_sources[0x16]	3907	1			T6	12		T7	16		T10	1
valid_sources[0x17]	2564	1			T7	4		T11	1		T12	1
valid_sources[0x18]	3441	1			T3	3		T7	10		T10	2
valid_sources[0x19]	3508	1			T3	1		T7	6		T10	2
valid_sources[0x1a]	3045	1			T7	11		T10	3		T12	3
valid_sources[0x1b]	4989	1			T6	2		T7	11		T11	7
valid_sources[0x1c]	4653	1			T7	10		T12	1		T21	4
valid_sources[0x1d]	2304	1			T3	2		T6	24		T7	9
valid_sources[0x1e]	3734	1			T7	13		T10	1		T12	2
valid_sources[0x1f]	8374	1			T3	1		T6	16		T7	8
valid_sources[0x20]	3638	1			T6	6		T7	6		T10	1
valid_sources[0x21]	2734	1			T3	1		T6	14		T7	8
valid_sources[0x22]	4506	1			T3	1		T6	3		T7	14
valid_sources[0x23]	4621	1			T7	20		T21	2		T60	5
valid_sources[0x24]	2547	1			T3	1		T7	9		T10	1
valid_sources[0x25]	3144	1			T3	1		T6	9		T7	11
valid_sources[0x26]	2891	1			T7	7		T10	2		T21	2
valid_sources[0x27]	2650	1			T6	15		T7	10		T10	1
valid_sources[0x28]	3658	1			T3	1		T6	7		T7	8
valid_sources[0x29]	3705	1			T7	5		T10	3		T60	5
valid_sources[0x2a]	2559	1			T3	2		T7	10		T10	1
valid_sources[0x2b]	2918	1			T7	2		T10	4		T12	1
valid_sources[0x2c]	3673	1			T3	1		T6	10		T7	3
valid_sources[0x2d]	3700	1			T3	1		T6	6		T7	11
valid_sources[0x2e]	2968	1			T3	1		T7	13		T10	3
valid_sources[0x2f]	2833	1			T3	1		T7	3		T10	1
valid_sources[0x30]	3075	1			T7	17		T10	3		T12	1
valid_sources[0x31]	3901	1			T7	7		T10	3		T12	4
valid_sources[0x32]	3211	1			T6	2		T7	14		T10	1
valid_sources[0x33]	2979	1			T7	11		T10	1		T11	1
valid_sources[0x34]	4605	1			T7	5		T10	2		T11	1
valid_sources[0x35]	3364	1			T3	1		T6	10		T7	11
valid_sources[0x36]	2689	1			T7	9		T10	2		T11	1
valid_sources[0x37]	2425	1			T3	2		T7	7		T11	2
valid_sources[0x38]	3425	1			T7	8		T10	1		T11	1
valid_sources[0x39]	4173	1			T7	9		T47	1		T21	1
valid_sources[0x3a]	2702	1			T7	6		T11	2		T12	1
valid_sources[0x3b]	3021	1			T6	19		T7	14		T10	1
valid_sources[0x3c]	3648	1			T6	14		T7	4		T10	4
valid_sources[0x3d]	5357	1			T3	1		T7	7		T11	2
valid_sources[0x3e]	2981	1			T3	1		T7	19		T10	1
valid_sources[0x3f]	3001	1			T3	1		T6	3		T7	10
valid_sources[0x40]	7833	1			T7	5		T10	1		T11	1
valid_sources[0x41]	3285	1			T3	2		T6	6		T7	11
valid_sources[0x42]	2966	1			T6	3		T7	4		T12	1
valid_sources[0x43]	2796	1			T7	9		T10	2		T12	2
valid_sources[0x44]	3267	1			T7	5		T10	1		T12	1
valid_sources[0x45]	3217	1			T3	1		T7	8		T10	1
valid_sources[0x46]	3346	1			T3	1		T6	1		T7	12
valid_sources[0x47]	3733	1			T6	28		T7	7		T10	2
valid_sources[0x48]	2912	1			T6	9		T7	12		T10	1
valid_sources[0x49]	5252	1			T7	11		T10	3		T12	1
valid_sources[0x4a]	3337	1			T7	10		T12	2		T21	2
valid_sources[0x4b]	3587	1			T7	8		T10	3		T12	4
valid_sources[0x4c]	3608	1			T7	13		T10	2		T11	1
valid_sources[0x4d]	3392	1			T7	7		T10	2		T11	2
valid_sources[0x4e]	4060	1			T7	10		T10	2		T21	2
valid_sources[0x4f]	3512	1			T7	5		T10	7		T11	2
valid_sources[0x50]	3151	1			T6	6		T7	4		T10	1
valid_sources[0x51]	3204	1			T3	1		T6	26		T7	10
valid_sources[0x52]	3145	1			T3	2		T7	8		T10	1
valid_sources[0x53]	3203	1			T7	7		T11	3		T12	2
valid_sources[0x54]	3566	1			T3	3		T7	8		T10	1
valid_sources[0x55]	2664	1			T3	1		T7	8		T11	1
valid_sources[0x56]	3606	1			T6	6		T7	15		T12	4
valid_sources[0x57]	3775	1			T6	1		T7	10		T10	1
valid_sources[0x58]	2714	1			T7	10		T10	1		T11	3
valid_sources[0x59]	3731	1			T3	2		T7	3		T10	1
valid_sources[0x5a]	3436	1			T3	2		T6	1		T7	9
valid_sources[0x5b]	2482	1			T6	3		T7	11		T10	3
valid_sources[0x5c]	2555	1			T7	13		T10	5		T60	3
valid_sources[0x5d]	2610	1			T3	1		T6	2		T7	7
valid_sources[0x5e]	2940	1			T3	1		T7	9		T10	2
valid_sources[0x5f]	3665	1			T3	1		T7	12		T11	2
valid_sources[0x60]	3130	1			T7	8		T11	1		T21	3
valid_sources[0x61]	3648	1			T3	1		T7	6		T12	2
valid_sources[0x62]	3446	1			T6	4		T7	10		T10	1
valid_sources[0x63]	3005	1			T6	6		T7	5		T10	2
valid_sources[0x64]	3971	1			T3	1		T7	8		T11	9
valid_sources[0x65]	2824	1			T7	8		T12	1		T60	5
valid_sources[0x66]	3784	1			T3	1		T7	6		T10	2
valid_sources[0x67]	6892	1			T6	3		T7	8		T10	5
valid_sources[0x68]	3436	1			T3	1		T7	7		T10	1
valid_sources[0x69]	3100	1			T6	3		T7	10		T21	3
valid_sources[0x6a]	3018	1			T7	8		T12	2		T21	2
valid_sources[0x6b]	2818	1			T6	12		T7	5		T10	2
valid_sources[0x6c]	2703	1			T6	29		T7	8		T10	2
valid_sources[0x6d]	3272	1			T3	3		T7	13		T10	5
valid_sources[0x6e]	3251	1			T7	13		T11	1		T12	3
valid_sources[0x6f]	2794	1			T3	1		T7	6		T11	1
valid_sources[0x70]	2907	1			T6	19		T7	7		T10	3
valid_sources[0x71]	3874	1			T7	8		T10	3		T12	3
valid_sources[0x72]	2649	1			T6	13		T7	10		T10	6
valid_sources[0x73]	2678	1			T3	1		T4	212		T7	5
valid_sources[0x74]	2901	1			T3	2		T7	4		T10	1
valid_sources[0x75]	2917	1			T3	1		T6	25		T7	8
valid_sources[0x76]	2945	1			T7	4		T11	1		T21	1
valid_sources[0x77]	3593	1			T7	6		T10	1		T60	6
valid_sources[0x78]	2597	1			T3	2		T6	15		T7	6
valid_sources[0x79]	3302	1			T6	3		T7	9		T10	3
valid_sources[0x7a]	2939	1			T6	12		T7	6		T10	3
valid_sources[0x7b]	2616	1			T6	18		T7	8		T10	2
valid_sources[0x7c]	2984	1			T2	379		T3	2		T7	10
valid_sources[0x7d]	3686	1			T3	1		T7	14		T10	1
valid_sources[0x7e]	2706	1			T3	1		T7	8		T10	3
valid_sources[0x7f]	2736	1			T6	2		T7	5		T10	1
valid_sources[0x80]	2913	1			T6	15		T7	5		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

220102

1

T2

97

T3

29

T4

38

values[0x0]

all_enables

biggest_size

72350

1

T2

36

T3

6

T4

14

values[0x1]

all_enables

biggest_size

38722

1

T2

19

T3

5

T4

9