Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_root_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_clean_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_out_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1193361	1163089	0	0
selKnown1	155968	125696	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193361	1163089	0	0
T1	135	71	0	0
T2	348	284	0	0
T3	449	385	0	0
T4	347	283	0	0
T5	662	598	0	0
T6	137	73	0	0
T7	2639	2575	0	0
T8	64	0	0	0
T9	148	84	0	0
T10	349	285	0	0
T11	0	283	0	0
T12	0	893	0	0
T13	0	9	0	0
T14	0	12	0	0
T23	0	12	0	0
T24	0	81	0	0
T25	0	27	0	0
T67	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	155968	125696	0	0
T2	128	64	0	0
T3	64	0	0	0
T4	128	64	0	0
T5	64	0	0	0
T6	64	0	0	0
T7	576	512	0	0
T8	64	0	0	0
T9	64	0	0	0
T10	128	64	0	0
T11	128	64	0	0
T21	0	64	0	0
T23	0	512	0	0
T38	0	448	0	0
T39	0	64	0	0
T79	0	64	0	0

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20140	19667	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20140	19667	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	9	8	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20202	19729	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20202	19729	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20959	20486	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20959	20486	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	8	7	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20976	20503	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20976	20503	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	9	8	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21004	20531	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21004	20531	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	8	7	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21086	20613	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21086	20613	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	9	8	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	7	6	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21102	20629	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21102	20629	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	11	10	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20140	19667	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20140	19667	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	9	8	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21127	20654	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21127	20654	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	11	10	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21186	20713	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21186	20713	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	12	11	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	7	6	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21246	20773	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	21246	20773	0	0
T1	2	1	0	0
T2	7	6	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	10	9	0	0
T6	13	12	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	20250	19777	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	20250	19777	0	0
T1	2	1	0	0
T2	6	5	0	0
T3	8	7	0	0
T4	6	5	0	0
T5	11	10	0	0
T6	1	0	0	0
T7	46	45	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	6	5	0	0
T11	0	5	0	0
T12	0	19	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6864	6391	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6864	6391	0	0
T1	6	5	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	5	4	0	0
T8	1	0	0	0
T9	14	13	0	0
T10	1	0	0	0
T13	0	1	0	0
T14	0	12	0	0
T23	0	12	0	0
T24	0	9	0	0
T25	0	27	0	0
T67	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8783	8310	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8783	8310	0	0
T1	5	4	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	10	9	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T7,T23,T38

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8358	7885	0	0
selKnown1	2437	1964	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8358	7885	0	0
T1	2	1	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	10	9	0	0
T6	1	0	0	0
T7	13	12	0	0
T8	1	0	0	0
T9	2	1	0	0
T10	2	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T24	0	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2437	1964	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	2	1	0	0
T5	1	0	0	0
T6	1	0	0	0
T7	9	8	0	0
T8	1	0	0	0
T9	1	0	0	0
T10	2	1	0	0
T11	2	1	0	0
T21	0	1	0	0
T23	0	8	0	0
T38	0	7	0	0
T39	0	1	0	0
T79	0	1	0	0