Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T60,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T60,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T60,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T60,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T60
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12438206	12601	0	0
gen_assertions[0].RstEnOn_A	12438206	921	0	0
gen_assertions[0].RstNOff_A	12438206	12601	0	0
gen_assertions[0].RstNOn_A	12438206	921	0	0
gen_assertions[1].RstEnOff_A	49752531	11397	0	0
gen_assertions[1].RstEnOn_A	49752531	874	0	0
gen_assertions[1].RstNOff_A	49752531	11397	0	0
gen_assertions[1].RstNOn_A	49752531	874	0	0
gen_assertions[2].RstEnOff_A	24877123	11425	0	0
gen_assertions[2].RstEnOn_A	24877123	839	0	0
gen_assertions[2].RstNOff_A	24877123	11425	0	0
gen_assertions[2].RstNOn_A	24877123	839	0	0
gen_assertions[3].RstEnOff_A	24877162	11507	0	0
gen_assertions[3].RstEnOn_A	24877162	915	0	0
gen_assertions[3].RstNOff_A	24877162	11507	0	0
gen_assertions[3].RstNOn_A	24877162	915	0	0
gen_assertions[4].RstEnOff_A	1568560	19803	0	0
gen_assertions[4].RstEnOn_A	1568560	951	0	0
gen_assertions[4].RstNOff_A	1568560	19803	0	0
gen_assertions[4].RstNOn_A	1568560	951	0	0
gen_assertions[5].RstEnOff_A	12438206	12769	0	0
gen_assertions[5].RstEnOn_A	12438206	953	0	0
gen_assertions[5].RstNOff_A	12438206	12769	0	0
gen_assertions[5].RstNOn_A	12438206	953	0	0
gen_assertions[6].RstEnOff_A	12438206	12828	0	0
gen_assertions[6].RstEnOn_A	12438206	1009	0	0
gen_assertions[6].RstNOff_A	12438206	12828	0	0
gen_assertions[6].RstNOn_A	12438206	1009	0	0
gen_assertions[7].RstEnOff_A	12438206	12888	0	0
gen_assertions[7].RstEnOn_A	12438206	1080	0	0
gen_assertions[7].RstNOff_A	12438206	12888	0	0
gen_assertions[7].RstNOn_A	12438206	1080	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12601	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	7	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	9	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	921	0	0
T3	2915	1	0	0
T4	3266	0	0	0
T5	7225	0	0	0
T6	10269	7	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T12	5560	3	0	0
T21	0	1	0	0
T22	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	5	0	0
T60	0	9	0	0
T80	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12601	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	7	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	9	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	921	0	0
T3	2915	1	0	0
T4	3266	0	0	0
T5	7225	0	0	0
T6	10269	7	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T12	5560	3	0	0
T21	0	1	0	0
T22	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	5	0	0
T60	0	9	0	0
T80	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49752531	11397	0	0
T2	22978	4	0	0
T3	11661	7	0	0
T4	13060	4	0	0
T5	28897	0	0	0
T6	41085	8	0	0
T7	107034	28	0	0
T8	5931	0	0	0
T9	14830	0	0	0
T10	22472	4	0	0
T11	17417	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	8	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49752531	874	0	0
T6	41085	8	0	0
T7	107034	0	0	0
T8	5931	0	0	0
T9	14830	0	0	0
T10	22472	0	0	0
T11	17417	0	0	0
T12	22242	0	0	0
T13	7891	0	0	0
T22	0	1	0	0
T24	29310	0	0	0
T36	0	2	0	0
T40	0	4	0	0
T47	6402	0	0	0
T60	0	8	0	0
T80	0	1	0	0
T81	0	5	0	0
T82	0	1	0	0
T83	0	8	0	0
T84	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49752531	11397	0	0
T2	22978	4	0	0
T3	11661	7	0	0
T4	13060	4	0	0
T5	28897	0	0	0
T6	41085	8	0	0
T7	107034	28	0	0
T8	5931	0	0	0
T9	14830	0	0	0
T10	22472	4	0	0
T11	17417	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	8	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49752531	874	0	0
T6	41085	8	0	0
T7	107034	0	0	0
T8	5931	0	0	0
T9	14830	0	0	0
T10	22472	0	0	0
T11	17417	0	0	0
T12	22242	0	0	0
T13	7891	0	0	0
T22	0	1	0	0
T24	29310	0	0	0
T36	0	2	0	0
T40	0	4	0	0
T47	6402	0	0	0
T60	0	8	0	0
T80	0	1	0	0
T81	0	5	0	0
T82	0	1	0	0
T83	0	8	0	0
T84	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877123	11425	0	0
T2	11487	4	0	0
T3	5831	7	0	0
T4	6531	4	0	0
T5	14453	0	0	0
T6	20542	7	0	0
T7	53525	28	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11237	4	0	0
T11	8708	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	9	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877123	839	0	0
T6	20542	7	0	0
T7	53525	0	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11237	0	0	0
T11	8708	0	0	0
T12	11120	0	0	0
T13	3945	0	0	0
T22	0	1	0	0
T24	14654	0	0	0
T36	0	4	0	0
T40	0	5	0	0
T47	3200	0	0	0
T60	0	9	0	0
T80	0	1	0	0
T81	0	5	0	0
T83	0	8	0	0
T85	0	5	0	0
T86	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877123	11425	0	0
T2	11487	4	0	0
T3	5831	7	0	0
T4	6531	4	0	0
T5	14453	0	0	0
T6	20542	7	0	0
T7	53525	28	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11237	4	0	0
T11	8708	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	9	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877123	839	0	0
T6	20542	7	0	0
T7	53525	0	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11237	0	0	0
T11	8708	0	0	0
T12	11120	0	0	0
T13	3945	0	0	0
T22	0	1	0	0
T24	14654	0	0	0
T36	0	4	0	0
T40	0	5	0	0
T47	3200	0	0	0
T60	0	9	0	0
T80	0	1	0	0
T81	0	5	0	0
T83	0	8	0	0
T85	0	5	0	0
T86	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877162	11507	0	0
T2	11488	4	0	0
T3	5830	7	0	0
T4	6529	4	0	0
T5	14451	0	0	0
T6	20542	8	0	0
T7	53520	28	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11232	5	0	0
T11	8709	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	10	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877162	915	0	0
T6	20542	8	0	0
T7	53520	0	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11232	1	0	0
T11	8709	0	0	0
T12	11120	0	0	0
T13	3945	0	0	0
T21	0	1	0	0
T24	14656	0	0	0
T36	0	6	0	0
T39	0	1	0	0
T40	0	7	0	0
T47	3200	0	0	0
T60	0	10	0	0
T81	0	8	0	0
T82	0	1	0	0
T83	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877162	11507	0	0
T2	11488	4	0	0
T3	5830	7	0	0
T4	6529	4	0	0
T5	14451	0	0	0
T6	20542	8	0	0
T7	53520	28	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11232	5	0	0
T11	8709	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	10	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24877162	915	0	0
T6	20542	8	0	0
T7	53520	0	0	0
T8	2965	0	0	0
T9	7415	0	0	0
T10	11232	1	0	0
T11	8709	0	0	0
T12	11120	0	0	0
T13	3945	0	0	0
T21	0	1	0	0
T24	14656	0	0	0
T36	0	6	0	0
T39	0	1	0	0
T40	0	7	0	0
T47	3200	0	0	0
T60	0	10	0	0
T81	0	8	0	0
T82	0	1	0	0
T83	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568560	19803	0	0
T1	343	2	0	0
T2	716	6	0	0
T3	363	8	0	0
T4	406	6	0	0
T5	905	3	0	0
T6	1283	11	0	0
T7	3428	46	0	0
T8	184	1	0	0
T9	463	2	0	0
T10	701	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568560	951	0	0
T6	1283	10	0	0
T7	3428	0	0	0
T8	184	0	0	0
T9	463	0	0	0
T10	701	0	0	0
T11	542	0	0	0
T12	694	0	0	0
T13	245	0	0	0
T24	919	0	0	0
T36	0	5	0	0
T40	0	9	0	0
T47	199	0	0	0
T60	0	10	0	0
T74	0	7	0	0
T81	0	9	0	0
T83	0	10	0	0
T85	0	6	0	0
T86	0	5	0	0
T87	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568560	19803	0	0
T1	343	2	0	0
T2	716	6	0	0
T3	363	8	0	0
T4	406	6	0	0
T5	905	3	0	0
T6	1283	11	0	0
T7	3428	46	0	0
T8	184	1	0	0
T9	463	2	0	0
T10	701	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568560	951	0	0
T6	1283	10	0	0
T7	3428	0	0	0
T8	184	0	0	0
T9	463	0	0	0
T10	701	0	0	0
T11	542	0	0	0
T12	694	0	0	0
T13	245	0	0	0
T24	919	0	0	0
T36	0	5	0	0
T40	0	9	0	0
T47	199	0	0	0
T60	0	10	0	0
T74	0	7	0	0
T81	0	9	0	0
T83	0	10	0	0
T85	0	6	0	0
T86	0	5	0	0
T87	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12769	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	10	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	13	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	953	0	0
T6	10269	10	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T12	5560	0	0	0
T13	1972	0	0	0
T24	7331	0	0	0
T36	0	8	0	0
T40	0	11	0	0
T47	1599	0	0	0
T60	0	13	0	0
T74	0	7	0	0
T76	0	23	0	0
T81	0	10	0	0
T83	0	12	0	0
T85	0	6	0	0
T86	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12769	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	10	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	13	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	953	0	0
T6	10269	10	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T12	5560	0	0	0
T13	1972	0	0	0
T24	7331	0	0	0
T36	0	8	0	0
T40	0	11	0	0
T47	1599	0	0	0
T60	0	13	0	0
T74	0	7	0	0
T76	0	23	0	0
T81	0	10	0	0
T83	0	12	0	0
T85	0	6	0	0
T86	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12828	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	11	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	5	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	16	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	1009	0	0
T6	10269	11	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	1	0	0
T11	4354	0	0	0
T12	5560	0	0	0
T13	1972	0	0	0
T21	0	1	0	0
T24	7331	0	0	0
T36	0	7	0	0
T40	0	12	0	0
T47	1599	0	0	0
T60	0	16	0	0
T81	0	10	0	0
T83	0	13	0	0
T85	0	7	0	0
T86	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12828	0	0
T2	5743	4	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	11	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	5	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	5	0	0
T60	0	16	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	1009	0	0
T6	10269	11	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	1	0	0
T11	4354	0	0	0
T12	5560	0	0	0
T13	1972	0	0	0
T21	0	1	0	0
T24	7331	0	0	0
T36	0	7	0	0
T40	0	12	0	0
T47	1599	0	0	0
T60	0	16	0	0
T81	0	10	0	0
T83	0	13	0	0
T85	0	7	0	0
T86	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12888	0	0
T2	5743	5	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	12	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	15	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	1080	0	0
T2	5743	1	0	0
T3	2915	0	0	0
T4	3266	0	0	0
T5	7225	0	0	0
T6	10269	12	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T36	0	9	0	0
T40	0	12	0	0
T60	0	15	0	0
T80	0	1	0	0
T81	0	13	0	0
T82	0	1	0	0
T83	0	15	0	0
T85	0	6	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	12888	0	0
T2	5743	5	0	0
T3	2915	7	0	0
T4	3266	4	0	0
T5	7225	0	0	0
T6	10269	12	0	0
T7	26759	33	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	4	0	0
T11	4354	4	0	0
T12	0	19	0	0
T21	0	4	0	0
T60	0	15	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12438206	1080	0	0
T2	5743	1	0	0
T3	2915	0	0	0
T4	3266	0	0	0
T5	7225	0	0	0
T6	10269	12	0	0
T7	26759	0	0	0
T8	1482	0	0	0
T9	3706	0	0	0
T10	5616	0	0	0
T11	4354	0	0	0
T36	0	9	0	0
T40	0	12	0	0
T60	0	15	0	0
T80	0	1	0	0
T81	0	13	0	0
T82	0	1	0	0
T83	0	15	0	0
T85	0	6	0	0