Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11906309	7770	0	0
alert_regwen_rd_A	11906309	6362	0	0
cpu_regwen_rd_A	11906309	6388	0	0
sw_rst_ctrl_n_0_rd_A	11906309	10835	0	0
sw_rst_ctrl_n_1_rd_A	11906309	10968	0	0
sw_rst_ctrl_n_2_rd_A	11906309	11001	0	0
sw_rst_ctrl_n_3_rd_A	11906309	10900	0	0
sw_rst_ctrl_n_4_rd_A	11906309	11106	0	0
sw_rst_ctrl_n_5_rd_A	11906309	11065	0	0
sw_rst_ctrl_n_6_rd_A	11906309	11002	0	0
sw_rst_ctrl_n_7_rd_A	11906309	11095	0	0
sw_rst_regwen_0_rd_A	11906309	6799	0	0
sw_rst_regwen_1_rd_A	11906309	6873	0	0
sw_rst_regwen_2_rd_A	11906309	6872	0	0
sw_rst_regwen_3_rd_A	11906309	6781	0	0
sw_rst_regwen_4_rd_A	11906309	6849	0	0
sw_rst_regwen_5_rd_A	11906309	6882	0	0
sw_rst_regwen_6_rd_A	11906309	6904	0	0
sw_rst_regwen_7_rd_A	11906309	6985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	7770	0	0
T62	19233	4	0	0
T63	16067	557	0	0
T66	4958	24	0	0
T70	8282	292	0	0
T71	20925	3	0	0
T90	3867	141	0	0
T91	26513	3	0	0
T92	2357	10	0	0
T93	3388	22	0	0
T96	2347	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6362	0	0
T108	109779	129	0	0
T109	0	46	0	0
T110	0	69	0	0
T114	35031	39	0	0
T115	20230	0	0	0
T136	0	46	0	0
T137	0	19	0	0
T138	0	92	0	0
T139	0	351	0	0
T140	0	206	0	0
T141	0	307	0	0
T142	5853	0	0	0
T143	5404	0	0	0
T144	2266	0	0	0
T145	13392	0	0	0
T146	6225	0	0	0
T147	167830	0	0	0
T148	4947	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6388	0	0
T108	109779	143	0	0
T109	0	46	0	0
T110	0	59	0	0
T114	35031	45	0	0
T115	20230	0	0	0
T136	0	51	0	0
T137	0	41	0	0
T138	0	74	0	0
T139	0	335	0	0
T140	0	201	0	0
T141	0	272	0	0
T142	5853	0	0	0
T143	5404	0	0	0
T144	2266	0	0	0
T145	13392	0	0	0
T146	6225	0	0	0
T147	167830	0	0	0
T148	4947	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	10835	0	0
T2	5455	17	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	96	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	7	0	0
T11	4161	0	0	0
T36	0	157	0	0
T37	0	22	0	0
T39	0	9	0	0
T77	0	210	0	0
T149	0	2	0	0
T150	0	7	0	0
T151	0	126	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	10968	0	0
T2	5455	11	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	156	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	6	0	0
T11	4161	0	0	0
T36	0	120	0	0
T37	0	12	0	0
T39	0	22	0	0
T77	0	216	0	0
T149	0	1	0	0
T150	0	9	0	0
T151	0	119	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	11001	0	0
T2	5455	9	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	98	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	5	0	0
T11	4161	0	0	0
T36	0	149	0	0
T37	0	19	0	0
T39	0	6	0	0
T77	0	230	0	0
T149	0	6	0	0
T150	0	12	0	0
T151	0	97	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	10900	0	0
T2	5455	4	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	130	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	14	0	0
T11	4161	0	0	0
T36	0	153	0	0
T37	0	16	0	0
T39	0	7	0	0
T77	0	233	0	0
T149	0	6	0	0
T150	0	15	0	0
T151	0	135	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	11106	0	0
T2	5455	11	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	111	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	5	0	0
T11	4161	0	0	0
T36	0	126	0	0
T37	0	17	0	0
T39	0	9	0	0
T77	0	234	0	0
T149	0	6	0	0
T150	0	12	0	0
T151	0	123	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	11065	0	0
T6	10180	102	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	13	0	0
T11	4161	0	0	0
T12	4221	0	0	0
T13	1881	0	0	0
T24	6885	0	0	0
T36	0	143	0	0
T37	0	15	0	0
T47	1533	0	0	0
T77	0	220	0	0
T114	0	53	0	0
T142	0	22	0	0
T145	0	221	0	0
T150	0	4	0	0
T151	0	132	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	11002	0	0
T2	5455	14	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	118	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	7	0	0
T11	4161	0	0	0
T36	0	142	0	0
T37	0	13	0	0
T39	0	6	0	0
T77	0	201	0	0
T149	0	4	0	0
T150	0	15	0	0
T151	0	99	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	11095	0	0
T2	5455	19	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	123	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	17	0	0
T11	4161	0	0	0
T36	0	142	0	0
T37	0	22	0	0
T77	0	231	0	0
T114	0	45	0	0
T149	0	6	0	0
T150	0	4	0	0
T151	0	107	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6799	0	0
T2	5455	3	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	14	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	1	0	0
T11	4161	0	0	0
T36	0	36	0	0
T39	0	2	0	0
T77	0	41	0	0
T114	0	48	0	0
T142	0	11	0	0
T150	0	8	0	0
T151	0	31	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6873	0	0
T2	5455	1	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	12	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	3	0	0
T11	4161	0	0	0
T36	0	32	0	0
T39	0	4	0	0
T77	0	25	0	0
T114	0	35	0	0
T142	0	14	0	0
T150	0	6	0	0
T151	0	34	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6872	0	0
T6	10180	7	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	6	0	0
T11	4161	0	0	0
T12	4221	0	0	0
T13	1881	0	0	0
T24	6885	0	0	0
T36	0	30	0	0
T39	0	9	0	0
T47	1533	0	0	0
T77	0	29	0	0
T114	0	50	0	0
T142	0	5	0	0
T145	0	31	0	0
T150	0	7	0	0
T151	0	46	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6781	0	0
T2	5455	3	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	9	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	7	0	0
T11	4161	0	0	0
T36	0	31	0	0
T77	0	36	0	0
T114	0	39	0	0
T142	0	9	0	0
T145	0	29	0	0
T150	0	3	0	0
T151	0	31	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6849	0	0
T2	5455	3	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	17	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	6	0	0
T11	4161	0	0	0
T36	0	41	0	0
T77	0	33	0	0
T114	0	29	0	0
T142	0	6	0	0
T145	0	33	0	0
T150	0	5	0	0
T151	0	36	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6882	0	0
T2	5455	7	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	10	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	9	0	0
T11	4161	0	0	0
T36	0	30	0	0
T39	0	11	0	0
T77	0	23	0	0
T114	0	44	0	0
T142	0	5	0	0
T150	0	13	0	0
T151	0	22	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6904	0	0
T6	10180	17	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	1	0	0
T11	4161	0	0	0
T12	4221	0	0	0
T13	1881	0	0	0
T24	6885	0	0	0
T36	0	44	0	0
T39	0	5	0	0
T47	1533	0	0	0
T77	0	21	0	0
T114	0	48	0	0
T142	0	8	0	0
T145	0	24	0	0
T150	0	13	0	0
T151	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11906309	6985	0	0
T2	5455	8	0	0
T3	2302	0	0	0
T4	3120	0	0	0
T5	6304	0	0	0
T6	10180	10	0	0
T7	23312	0	0	0
T8	1392	0	0	0
T9	3544	0	0	0
T10	5375	0	0	0
T11	4161	0	0	0
T36	0	17	0	0
T39	0	13	0	0
T77	0	37	0	0
T114	0	45	0	0
T142	0	3	0	0
T145	0	31	0	0
T150	0	5	0	0
T151	0	39	0	0