| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T518 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3449047306 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 75855814 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2805561176 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 159786839 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.513520966 | Oct 09 06:05:51 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 183533112 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2551253856 | Oct 09 06:05:58 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 223785977 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.333765813 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 142535109 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3669461174 | Oct 09 06:05:51 AM UTC 24 | Oct 09 06:06:01 AM UTC 24 | 157284300 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2243438632 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 111819947 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.771141427 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 213042325 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2132808457 | Oct 09 06:05:57 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 199607542 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.457368475 | Oct 09 06:05:51 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 344819491 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2467440746 | Oct 09 06:05:52 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 773460752 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2270584439 | Oct 09 06:05:51 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 792698634 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3618837286 | Oct 09 06:05:57 AM UTC 24 | Oct 09 06:06:02 AM UTC 24 | 881785837 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2682793730 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:03 AM UTC 24 | 903881046 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1822410026 | Oct 09 06:05:59 AM UTC 24 | Oct 09 06:06:03 AM UTC 24 | 917505000 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2258172992 | Oct 09 06:05:50 AM UTC 24 | Oct 09 06:06:05 AM UTC 24 | 91871178 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2738080948 | Oct 09 06:05:50 AM UTC 24 | Oct 09 06:06:05 AM UTC 24 | 141526225 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1641753797 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:05 AM UTC 24 | 61325831 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.607100961 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:05 AM UTC 24 | 188950803 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3391208643 | Oct 09 06:05:51 AM UTC 24 | Oct 09 06:06:07 AM UTC 24 | 1532913393 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3220372064 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:07 AM UTC 24 | 458695362 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3550855073 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:07 AM UTC 24 | 878669623 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1061685806 | Oct 09 06:05:56 AM UTC 24 | Oct 09 06:06:09 AM UTC 24 | 2293391532 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.336936358 | Oct 09 06:05:50 AM UTC 24 | Oct 09 06:06:09 AM UTC 24 | 1195798310 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2724874090 | Oct 09 06:06:09 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 78281559 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2033403449 | Oct 09 06:06:05 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 221373938 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1854164385 | Oct 09 06:06:05 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 127484099 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4242430782 | Oct 09 06:06:08 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 150322154 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3611452694 | Oct 09 06:06:07 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 222416068 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2119230960 | Oct 09 06:06:05 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 491574015 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2530090190 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 64241231 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3641973637 | Oct 09 06:06:09 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 184569045 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3001606166 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 77233849 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.837875805 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 72409907 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3031110508 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 123398526 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.971025570 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:11 AM UTC 24 | 128991139 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.280745274 | Oct 09 06:06:10 AM UTC 24 | Oct 09 06:06:12 AM UTC 24 | 88497194 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2424081672 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:12 AM UTC 24 | 177612383 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.70784713 | Oct 09 06:06:09 AM UTC 24 | Oct 09 06:06:12 AM UTC 24 | 785667450 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3857759091 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:12 AM UTC 24 | 497738280 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3842095385 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:13 AM UTC 24 | 397525439 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.673108457 | Oct 09 06:06:06 AM UTC 24 | Oct 09 06:06:14 AM UTC 24 | 581411949 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3568578211 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:15 AM UTC 24 | 56952546 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4204747250 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 115482941 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3032594555 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 90158254 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2043962262 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 73117058 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3023953915 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 66749282 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2698743682 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:20 AM UTC 24 | 61745775 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4108939866 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 84438883 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2732649505 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 139242223 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2379344478 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 83565193 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2580544648 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 82447214 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1873814266 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 84030246 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1260635320 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 139942146 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2294609611 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 132112062 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.291787024 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 230328026 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3113859937 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 139441077 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158658086 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 212787582 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1394913594 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 152984869 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1135486020 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 160492051 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1723313982 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 101482077 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2191694342 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 495246499 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1933669781 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 229410342 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.587252108 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:16 AM UTC 24 | 482660335 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2186048639 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 209743611 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3728883163 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 203112425 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3747339853 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 297029662 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.678781014 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 168958263 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.690943058 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 396746794 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1215292101 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:17 AM UTC 24 | 945671277 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1965208206 | Oct 09 06:06:03 AM UTC 24 | Oct 09 06:06:18 AM UTC 24 | 882030289 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3456047929 | Oct 09 06:06:02 AM UTC 24 | Oct 09 06:06:18 AM UTC 24 | 539870399 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3339871691 | Oct 09 06:06:01 AM UTC 24 | Oct 09 06:06:20 AM UTC 24 | 220365688 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1023986711 | Oct 09 06:06:11 AM UTC 24 | Oct 09 06:06:21 AM UTC 24 | 487532900 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.1865186581 | Oct 09 06:06:11 AM UTC 24 | Oct 09 06:06:21 AM UTC 24 | 320704737 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2553709646 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:26 AM UTC 24 | 72527209 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1427548541 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:27 AM UTC 24 | 158321378 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1533635319 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:27 AM UTC 24 | 233406970 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3529188204 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:28 AM UTC 24 | 329698889 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2190133344 | Oct 09 06:06:04 AM UTC 24 | Oct 09 06:06:28 AM UTC 24 | 914750958 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2101451529 | Oct 09 06:05:55 AM UTC 24 | Oct 09 06:06:31 AM UTC 24 | 212357496 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.462085479 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:32 AM UTC 24 | 85779247 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1339592222 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:32 AM UTC 24 | 79207343 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2365992541 | Oct 09 06:06:12 AM UTC 24 | Oct 09 06:06:32 AM UTC 24 | 141994000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.682474159 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 234331593 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 06:03:53 AM UTC 24 |
| Finished | Oct 09 06:03:56 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682474159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.682474159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.1932800308 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 397866348 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:03:59 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932800308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1932800308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.335634765 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1384135025 ps |
| CPU time | 5.74 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:04:01 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335634765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.335634765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.470355979 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 843406362 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 06:05:48 AM UTC 24 |
| Finished | Oct 09 06:05:53 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470355979 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.470355979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.307553777 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8579316821 ps |
| CPU time | 13.49 seconds |
| Started | Oct 09 06:03:56 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 243672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307553777 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.307553777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2371912370 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1979594089 ps |
| CPU time | 8.17 seconds |
| Started | Oct 09 06:03:51 AM UTC 24 |
| Finished | Oct 09 06:04:00 AM UTC 24 |
| Peak memory | 244492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371912370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2371912370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4213370472 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 672494174 ps |
| CPU time | 3.52 seconds |
| Started | Oct 09 06:05:48 AM UTC 24 |
| Finished | Oct 09 06:05:54 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213370472 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4213370472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.2741547785 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 158569977 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 210224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741547785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2741547785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3641951 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1281417239 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:04:03 AM UTC 24 |
| Peak memory | 243496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3641951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.326153895 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2658138655 ps |
| CPU time | 11.95 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326153895 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.326153895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2480390612 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 136357096 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 06:03:50 AM UTC 24 |
| Finished | Oct 09 06:03:53 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480390612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2480390612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.4133223582 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 62022612 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 06:03:53 AM UTC 24 |
| Finished | Oct 09 06:03:55 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133223582 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4133223582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3653374895 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1673335108 ps |
| CPU time | 5.79 seconds |
| Started | Oct 09 06:04:16 AM UTC 24 |
| Finished | Oct 09 06:04:23 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653374895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3653374895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3950325626 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1985217762 ps |
| CPU time | 6.89 seconds |
| Started | Oct 09 06:04:04 AM UTC 24 |
| Finished | Oct 09 06:04:12 AM UTC 24 |
| Peak memory | 243724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950325626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3950325626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2682793730 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 903881046 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:03 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682793730 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.2682793730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1192992588 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 114749756 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:03:49 AM UTC 24 |
| Finished | Oct 09 06:03:51 AM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192992588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1192992588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1822410026 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 917505000 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 06:05:59 AM UTC 24 |
| Finished | Oct 09 06:06:03 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822410026 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.1822410026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1200154984 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 8096212850 ps |
| CPU time | 27.33 seconds |
| Started | Oct 09 06:03:55 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200154984 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1200154984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.170478271 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 348123516 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 06:05:42 AM UTC 24 |
| Finished | Oct 09 06:05:57 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170478271 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.170478271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2190133344 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 914750958 ps |
| CPU time | 2.74 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:28 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190133344 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.2190133344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2258172992 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 91871178 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 06:05:50 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258172992 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2258172992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4243328785 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1980763024 ps |
| CPU time | 8.78 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:04:04 AM UTC 24 |
| Peak memory | 243664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243328785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4243328785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2270584439 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 792698634 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270584439 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2270584439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1335340937 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 154740350 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 06:05:47 AM UTC 24 |
| Finished | Oct 09 06:05:57 AM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335340937 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1335340937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3624685872 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1168490134 ps |
| CPU time | 4.51 seconds |
| Started | Oct 09 06:05:46 AM UTC 24 |
| Finished | Oct 09 06:05:54 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624685872 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3624685872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1156618755 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 96566895 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 06:05:44 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156618755 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1156618755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2418957449 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 212616315 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 06:05:47 AM UTC 24 |
| Finished | Oct 09 06:05:56 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2418957449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w ith_rand_reset.2418957449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.706583748 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 72940416 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 06:05:46 AM UTC 24 |
| Finished | Oct 09 06:05:51 AM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706583748 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.706583748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4009928320 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 913920811 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 06:05:44 AM UTC 24 |
| Finished | Oct 09 06:05:58 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009928320 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.4009928320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3669461174 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 157284300 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669461174 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3669461174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.336936358 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1195798310 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 06:05:50 AM UTC 24 |
| Finished | Oct 09 06:06:09 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336936358 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.336936358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2738080948 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 141526225 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 06:05:50 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738080948 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2738080948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2984371133 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 164958092 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 217680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2984371133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.2984371133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.731446766 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 133824917 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731446766 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.731446766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1260635320 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 139942146 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1260635320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1260635320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3032594555 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 90158254 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032594555 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3032594555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158658086 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 212787582 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 207760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158658086 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.2158658086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3456047929 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 539870399 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:18 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456047929 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3456047929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2191694342 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 495246499 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191694342 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.2191694342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3113859937 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 139441077 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3113859937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.3113859937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2580544648 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 82447214 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580544648 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2580544648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1723313982 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 101482077 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723313982 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1723313982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3747339853 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 297029662 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747339853 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3747339853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1965208206 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 882030289 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 06:06:03 AM UTC 24 |
| Finished | Oct 09 06:06:18 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965208206 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.1965208206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1427548541 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 158321378 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:27 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1427548541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.1427548541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2698743682 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 61745775 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:20 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698743682 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2698743682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2186048639 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 209743611 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 208088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186048639 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.2186048639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.678781014 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 168958263 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678781014 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.678781014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2033403449 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 221373938 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:06:05 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2033403449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.2033403449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2553709646 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 72527209 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:26 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553709646 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2553709646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1533635319 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 233406970 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:27 AM UTC 24 |
| Peak memory | 208132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533635319 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.1533635319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3529188204 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 329698889 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 06:06:04 AM UTC 24 |
| Finished | Oct 09 06:06:28 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529188204 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3529188204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2424081672 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 177612383 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2424081672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.2424081672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3001606166 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 77233849 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001606166 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3001606166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.971025570 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 128991139 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 207920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971025570 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.971025570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1854164385 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 127484099 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 06:06:05 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854164385 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1854164385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2119230960 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 491574015 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 06:06:05 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 207976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119230960 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.2119230960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4242430782 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 150322154 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:06:08 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 217172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4242430782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.4242430782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.837875805 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 72409907 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837875805 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.837875805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3611452694 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 222416068 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:06:07 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611452694 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3611452694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.673108457 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 581411949 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:14 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673108457 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.673108457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3857759091 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 497738280 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 06:06:06 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 208020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857759091 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3857759091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2997732163 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 167156827 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 06:06:10 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 217764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2997732163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.2997732163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2724874090 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 78281559 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 06:06:09 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724874090 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2724874090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.280745274 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 88497194 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 06:06:10 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280745274 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.280745274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3641973637 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 184569045 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:06:09 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 219336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641973637 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3641973637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.70784713 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 785667450 ps |
| CPU time | 2.48 seconds |
| Started | Oct 09 06:06:09 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70784713 -assert nopostproc +UVM_TESTNAM E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.70784713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2365992541 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 141994000 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:32 AM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2365992541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.2365992541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.462085479 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 85779247 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:32 AM UTC 24 |
| Peak memory | 207592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462085479 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.462085479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1339592222 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 79207343 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:32 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339592222 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.1339592222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.1865186581 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 320704737 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 06:06:11 AM UTC 24 |
| Finished | Oct 09 06:06:21 AM UTC 24 |
| Peak memory | 217712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865186581 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1865186581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1023986711 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 487532900 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 06:06:11 AM UTC 24 |
| Finished | Oct 09 06:06:21 AM UTC 24 |
| Peak memory | 207976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023986711 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1023986711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2732649505 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 139242223 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2732649505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.2732649505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3568578211 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 56952546 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:15 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568578211 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3568578211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4108939866 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 84438883 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108939866 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.4108939866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.291787024 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 230328026 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291787024 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.291787024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1215292101 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 945671277 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215292101 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.1215292101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1933669781 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 229410342 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1933669781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.1933669781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3023953915 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 66749282 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023953915 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3023953915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2294609611 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 132112062 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294609611 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.2294609611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.690943058 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 396746794 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690943058 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.690943058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.587252108 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 482660335 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 06:06:12 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587252108 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.587252108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.457368475 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 344819491 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457368475 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.457368475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3391208643 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1532913393 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:07 AM UTC 24 |
| Peak memory | 208092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391208643 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3391208643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2551380906 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 94450677 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551380906 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2551380906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2827712495 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 101824286 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2827712495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2827712495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2901936710 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 64246152 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 206304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901936710 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2901936710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2139944513 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 145194433 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139944513 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2139944513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1121683862 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 237874464 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121683862 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1121683862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2101451529 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 212357496 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:05:55 AM UTC 24 |
| Finished | Oct 09 06:06:31 AM UTC 24 |
| Peak memory | 207964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101451529 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2101451529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.283588277 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 492496566 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 06:05:54 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283588277 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.283588277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.202878059 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 83199514 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 06:05:52 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202878059 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.202878059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2805561176 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 159786839 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2805561176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.2805561176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.1960890973 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 76747330 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 06:05:53 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960890973 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1960890973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1773589282 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 111939017 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:05:55 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773589282 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1773589282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.513520966 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 183533112 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 06:05:51 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513520966 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.513520966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2467440746 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 773460752 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 06:05:52 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467440746 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.2467440746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2243438632 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 111819947 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243438632 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2243438632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1061685806 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2293391532 ps |
| CPU time | 8.3 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:09 AM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061685806 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1061685806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.333765813 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 142535109 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333765813 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.333765813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4176687807 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 104237553 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 216440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4176687807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.4176687807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3449047306 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 75855814 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449047306 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3449047306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1370322815 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 159167006 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 206500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370322815 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.1370322815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.771141427 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 213042325 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 06:05:56 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771141427 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.771141427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2071963782 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 147191586 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2071963782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.2071963782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.4270476530 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 80658443 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270476530 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4270476530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.785799963 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 87202254 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785799963 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.785799963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2132808457 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 199607542 ps |
| CPU time | 2.59 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 221836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132808457 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2132808457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3618837286 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 881785837 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 06:05:57 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618837286 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.3618837286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3728883163 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 203112425 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:17 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3728883163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.3728883163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2379344478 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 83565193 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379344478 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2379344478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1135486020 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 160492051 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135486020 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.1135486020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2551253856 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 223785977 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 06:05:58 AM UTC 24 |
| Finished | Oct 09 06:06:01 AM UTC 24 |
| Peak memory | 217868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551253856 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2551253856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3339871691 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 220365688 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:20 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3339871691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.3339871691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1873814266 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 84030246 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873814266 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1873814266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1394913594 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 152984869 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 06:06:01 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394913594 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.1394913594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.607100961 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 188950803 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=607100961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_wi th_rand_reset.607100961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2530090190 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 64241231 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530090190 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2530090190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3031110508 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 123398526 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:11 AM UTC 24 |
| Peak memory | 208068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031110508 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3031110508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3842095385 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 397525439 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:13 AM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842095385 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3842095385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.684313293 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1188742278 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:13 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684313293 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.684313293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4204747250 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 115482941 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4204747250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.4204747250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1641753797 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 61325831 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641753797 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1641753797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2043962262 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 73117058 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:16 AM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043962262 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2043962262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3220372064 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 458695362 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:07 AM UTC 24 |
| Peak memory | 217832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220372064 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3220372064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3550855073 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 878669623 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 06:06:02 AM UTC 24 |
| Finished | Oct 09 06:06:07 AM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550855073 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3550855073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2234631742 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 302708565 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 06:03:51 AM UTC 24 |
| Finished | Oct 09 06:03:54 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234631742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2234631742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.3136715391 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1143379031 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 06:03:49 AM UTC 24 |
| Finished | Oct 09 06:03:55 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136715391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3136715391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.1971054852 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 17738705598 ps |
| CPU time | 28.58 seconds |
| Started | Oct 09 06:03:53 AM UTC 24 |
| Finished | Oct 09 06:04:23 AM UTC 24 |
| Peak memory | 243632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971054852 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1971054852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.965890684 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 239622011 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 06:03:49 AM UTC 24 |
| Finished | Oct 09 06:03:52 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965890684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.965890684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.609821409 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1606502364 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 06:03:52 AM UTC 24 |
| Finished | Oct 09 06:03:59 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609821409 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.609821409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1945927585 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 428197325 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 06:03:50 AM UTC 24 |
| Finished | Oct 09 06:03:54 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945927585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1945927585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.2240826745 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 121701735 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 06:03:50 AM UTC 24 |
| Finished | Oct 09 06:03:53 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240826745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2240826745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.410200846 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 66914181 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 06:03:56 AM UTC 24 |
| Finished | Oct 09 06:03:58 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410200846 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.410200846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.815370116 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 306918000 ps |
| CPU time | 1.89 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:03:58 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815370116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.815370116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.2601536742 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 154694851 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 06:03:53 AM UTC 24 |
| Finished | Oct 09 06:03:56 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601536742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2601536742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2066722376 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 181690345 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:03:57 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066722376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2066722376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3822558645 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 231905644 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 06:03:54 AM UTC 24 |
| Finished | Oct 09 06:03:57 AM UTC 24 |
| Peak memory | 210224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822558645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3822558645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1031814485 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 77484167 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031814485 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1031814485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.2759602265 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1968128619 ps |
| CPU time | 7.27 seconds |
| Started | Oct 09 06:04:13 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 243544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759602265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2759602265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4156284620 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 302824164 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156284620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4156284620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2036304911 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 99036874 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:14 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036304911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2036304911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3392612998 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1106207892 ps |
| CPU time | 5.37 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392612998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3392612998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3034295706 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 188622695 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 06:04:13 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034295706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3034295706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3683412593 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 250231464 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:15 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683412593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3683412593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.678308468 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2063626768 ps |
| CPU time | 10.44 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678308468 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.678308468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.18505796 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 114359057 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 06:04:13 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18505796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.18505796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2384862936 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 72827253 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:14 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384862936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2384862936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3209364199 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 55021630 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209364199 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3209364199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.2021150261 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1272287618 ps |
| CPU time | 5.44 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 244528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021150261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2021150261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4140770771 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 303901062 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:18 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140770771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4140770771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.2531587650 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 209620209 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531587650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2531587650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3330298976 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1776297038 ps |
| CPU time | 9.76 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330298976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3330298976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.878093896 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 169238217 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878093896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.878093896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.1842977786 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 118485057 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842977786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1842977786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.3080805935 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2235471262 ps |
| CPU time | 8.56 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080805935 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3080805935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2677620758 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 143158048 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677620758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2677620758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.1204667162 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 99166247 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:04:14 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204667162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1204667162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3722579877 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 85743375 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722579877 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3722579877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.1857325454 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1976756343 ps |
| CPU time | 6.82 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 253832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857325454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1857325454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2631136620 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 302077576 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 239280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631136620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2631136620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3077956076 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 121572778 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:18 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077956076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3077956076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.605367097 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 107622616 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605367097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.605367097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.714363691 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 117699777 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 06:04:15 AM UTC 24 |
| Finished | Oct 09 06:04:18 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714363691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.714363691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.3793009585 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5112702815 ps |
| CPU time | 21.15 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793009585 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3793009585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2798725788 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 331859983 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 220364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798725788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2798725788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.204027308 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 170071860 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:16 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204027308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.204027308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2023425224 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 92621636 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:21 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023425224 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2023425224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3342073179 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1269502246 ps |
| CPU time | 5.85 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 243952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342073179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3342073179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.270332726 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 302565707 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:21 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270332726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.270332726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.3423363635 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 184610970 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423363635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3423363635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.528520872 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1093330099 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528520872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.528520872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3808119356 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 153997846 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808119356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3808119356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.1576200945 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 114355842 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:04:17 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576200945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1576200945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1839661954 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 14373394194 ps |
| CPU time | 45.7 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839661954 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1839661954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.257893025 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 351027770 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:21 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257893025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.257893025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.3658989233 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 182825153 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:18 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658989233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3658989233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.207125439 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 55940333 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:23 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207125439 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.207125439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.323911836 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2462389018 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 06:04:20 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 243796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323911836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.323911836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3113885787 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 301245490 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 06:04:20 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113885787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3113885787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.2300585837 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 159205582 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:21 AM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300585837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2300585837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.3567695513 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 868130922 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567695513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3567695513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1332655232 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 151164703 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332655232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1332655232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.1498186062 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 107697840 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498186062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1498186062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3708075998 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 7115513274 ps |
| CPU time | 23 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708075998 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3708075998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.4187858717 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 559034426 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187858717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4187858717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.1230012464 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 155405006 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:19 AM UTC 24 |
| Finished | Oct 09 06:04:22 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230012464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1230012464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2929717904 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 60988201 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929717904 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2929717904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.2154638111 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1273208141 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 244380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154638111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2154638111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1236816708 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 302149066 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 240040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236816708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1236816708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3767348464 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 233203153 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767348464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3767348464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.3328190429 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 959910661 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:27 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328190429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3328190429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1326087155 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 155205344 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:23 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326087155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1326087155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.3588704948 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 254236589 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:23 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588704948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3588704948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1559772664 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2760058485 ps |
| CPU time | 11.21 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559772664 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1559772664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.2860738089 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 263400943 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860738089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2860738089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.164848964 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 128149581 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 06:04:21 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164848964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.164848964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.3126834962 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 57111135 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:26 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126834962 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3126834962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3174921116 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1277454246 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:30 AM UTC 24 |
| Peak memory | 244396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174921116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3174921116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4266320652 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 302583517 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:26 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266320652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4266320652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.4106456185 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 212166410 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106456185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4106456185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1954757553 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 761910901 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954757553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1954757553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2255386131 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 161452329 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:26 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255386131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2255386131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.721126005 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 200664740 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721126005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.721126005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3609325284 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4997397472 ps |
| CPU time | 21.71 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609325284 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3609325284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.63313146 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 139275415 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 06:04:24 AM UTC 24 |
| Finished | Oct 09 06:04:26 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63313146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.63313146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.759137635 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 79952683 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:04:22 AM UTC 24 |
| Finished | Oct 09 06:04:25 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759137635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.759137635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.4129407848 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 67286111 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129407848 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4129407848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2153866553 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1981007119 ps |
| CPU time | 6.74 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 244408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153866553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2153866553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3643306699 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 301872721 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643306699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3643306699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.2705178215 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 198031322 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:27 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705178215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2705178215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.4074863128 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1754088671 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074863128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4074863128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2399648713 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 173108912 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399648713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2399648713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3330439600 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 123397436 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:27 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330439600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3330439600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.3078769316 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 11367377671 ps |
| CPU time | 35.61 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:05:02 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078769316 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3078769316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3244537937 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 254901388 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244537937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3244537937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.640836418 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 177237727 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640836418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.640836418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.2272302689 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 83405298 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272302689 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2272302689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.1248808571 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1971501913 ps |
| CPU time | 7.27 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 244020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248808571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1248808571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2508713547 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 302785650 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508713547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2508713547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.3203684373 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 112787662 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:27 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203684373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3203684373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1694308512 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1484633122 ps |
| CPU time | 5.96 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694308512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1694308512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1532217672 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 145330584 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532217672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1532217672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.1305432795 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 244199725 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305432795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1305432795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.390890757 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4746699842 ps |
| CPU time | 19.7 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390890757 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.390890757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.1712985823 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 462818683 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 06:04:26 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712985823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1712985823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.2007518825 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 142825030 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:04:25 AM UTC 24 |
| Finished | Oct 09 06:04:28 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007518825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2007518825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.4264218093 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 61328957 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:30 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264218093 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4264218093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.2486907152 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2244891133 ps |
| CPU time | 8.57 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:38 AM UTC 24 |
| Peak memory | 244132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486907152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2486907152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1164496732 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 301870258 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:31 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164496732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1164496732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.3911403167 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 231622092 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911403167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3911403167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.1111898957 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1740213868 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111898957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1111898957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4144033215 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 156324307 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:30 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144033215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4144033215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1177635083 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 259272883 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:30 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177635083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1177635083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.207470845 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 10712696221 ps |
| CPU time | 32.26 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:05:02 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207470845 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.207470845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.2900146257 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 369957927 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:32 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900146257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2900146257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.1575893115 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 120414747 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:27 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575893115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1575893115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.4291349554 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 60907666 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:00 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291349554 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4291349554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3307007407 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 301449297 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:04:00 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307007407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3307007407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3886478052 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 82401716 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 06:03:56 AM UTC 24 |
| Finished | Oct 09 06:03:58 AM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886478052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3886478052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.2166242675 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1256086439 ps |
| CPU time | 6.27 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:04:04 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166242675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2166242675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.138020366 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 16552629376 ps |
| CPU time | 29.24 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:29 AM UTC 24 |
| Peak memory | 244332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138020366 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.138020366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1814267403 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 146499906 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:03:59 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814267403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1814267403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3612941374 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 119606067 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 06:03:56 AM UTC 24 |
| Finished | Oct 09 06:03:58 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612941374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3612941374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.513277759 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 396750677 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:04:00 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513277759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.513277759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.410449555 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 103328327 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 06:03:57 AM UTC 24 |
| Finished | Oct 09 06:03:59 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410449555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.410449555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3433279659 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 67699805 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:32 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433279659 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3433279659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.1368380083 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1962553258 ps |
| CPU time | 6.92 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:38 AM UTC 24 |
| Peak memory | 244228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368380083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1368380083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2968679699 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 302084490 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968679699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2968679699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.3619606907 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 187154165 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:31 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619606907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3619606907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.2444631701 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1667759234 ps |
| CPU time | 5.95 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:36 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444631701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2444631701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3577250217 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 104079512 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577250217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3577250217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.463627985 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 110112546 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 06:04:28 AM UTC 24 |
| Finished | Oct 09 06:04:31 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463627985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.463627985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.2634097430 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 121115776 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:32 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634097430 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2634097430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.3954989630 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 150498271 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954989630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3954989630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.325626802 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 139289329 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 06:04:29 AM UTC 24 |
| Finished | Oct 09 06:04:31 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325626802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.325626802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.2568505049 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 85908713 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568505049 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2568505049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.2218721484 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1263999186 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218721484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2218721484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3790996232 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 301703084 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:04:31 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790996232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3790996232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.510479997 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 167950532 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510479997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.510479997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.3456081089 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 815461550 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:36 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456081089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3456081089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.871815102 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 109441709 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871815102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.871815102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2667074383 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 186030919 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667074383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2667074383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2025565173 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2714127848 ps |
| CPU time | 9.02 seconds |
| Started | Oct 09 06:04:31 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025565173 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2025565173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.252596171 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 117866132 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252596171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.252596171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.122816108 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 170272317 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:30 AM UTC 24 |
| Finished | Oct 09 06:04:33 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122816108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.122816108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1533722283 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 73781986 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533722283 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1533722283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3240286536 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1971298809 ps |
| CPU time | 7.45 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 244476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240286536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3240286536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2701256519 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 307655315 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701256519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2701256519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.3986313334 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 113483093 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986313334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3986313334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.3486719160 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 706545955 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486719160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3486719160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3565063393 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 153705172 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565063393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3565063393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.4130018360 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 201943318 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130018360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4130018360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.1499617041 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 10735236363 ps |
| CPU time | 34.43 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:05:09 AM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499617041 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1499617041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.2433971651 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 149498417 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433971651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2433971651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.1617239377 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 190485483 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 06:04:32 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617239377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1617239377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.2812254340 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 80943816 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812254340 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2812254340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.709840541 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1957704777 ps |
| CPU time | 7.09 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:43 AM UTC 24 |
| Peak memory | 243772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709840541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.709840541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2063455590 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 301994739 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063455590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2063455590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3987387527 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 72689858 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:04:35 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987387527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3987387527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.1300873077 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1997218904 ps |
| CPU time | 6.62 seconds |
| Started | Oct 09 06:04:34 AM UTC 24 |
| Finished | Oct 09 06:04:43 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300873077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1300873077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.124958818 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 139116218 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124958818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.124958818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.4128808306 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 194107544 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 06:04:33 AM UTC 24 |
| Finished | Oct 09 06:04:36 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128808306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4128808306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3583436670 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 6732787773 ps |
| CPU time | 22.86 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583436670 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3583436670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.266407814 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 265028438 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 06:04:34 AM UTC 24 |
| Finished | Oct 09 06:04:38 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266407814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.266407814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.2697975372 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 119109409 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:04:34 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697975372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2697975372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.3161552503 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 76147235 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161552503 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3161552503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.4104027735 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1278213579 ps |
| CPU time | 5.49 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 244460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104027735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4104027735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3095735581 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 302369284 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095735581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3095735581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.3306169401 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 206118087 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:38 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306169401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3306169401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.1179681297 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 934084155 ps |
| CPU time | 5.29 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179681297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1179681297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.858108533 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 93820748 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858108533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.858108533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.1394930201 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 122907305 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:37 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394930201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1394930201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3357478874 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 13823026310 ps |
| CPU time | 42.24 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:05:21 AM UTC 24 |
| Peak memory | 220512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357478874 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3357478874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.1321386225 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 128071681 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:40 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321386225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1321386225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.1597586131 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 164781985 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 06:04:35 AM UTC 24 |
| Finished | Oct 09 06:04:38 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597586131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1597586131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3965106064 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 62905864 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:40 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965106064 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3965106064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.1534872045 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2458094005 ps |
| CPU time | 9 seconds |
| Started | Oct 09 06:04:37 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 244544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534872045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1534872045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3522681304 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 302358055 ps |
| CPU time | 1.89 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 239292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522681304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3522681304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2620138504 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 86776533 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620138504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2620138504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.2210423986 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 797125057 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210423986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2210423986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2703064807 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 102688369 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 06:04:37 AM UTC 24 |
| Finished | Oct 09 06:04:39 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703064807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2703064807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.3054438494 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 196941795 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 06:04:36 AM UTC 24 |
| Finished | Oct 09 06:04:40 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054438494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3054438494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.3655560648 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3775972381 ps |
| CPU time | 15.49 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655560648 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3655560648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3875656132 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 460112386 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 06:04:37 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875656132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3875656132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3313638858 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 201125670 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 06:04:37 AM UTC 24 |
| Finished | Oct 09 06:04:40 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313638858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3313638858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.4201583419 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 69449540 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 06:04:39 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201583419 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4201583419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.1869316574 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1268169455 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 06:04:39 AM UTC 24 |
| Finished | Oct 09 06:04:46 AM UTC 24 |
| Peak memory | 244272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869316574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1869316574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2884942956 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 301525123 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 06:04:39 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884942956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2884942956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.2752270741 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 186490395 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752270741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2752270741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.695671944 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 723586154 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:43 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695671944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.695671944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1173424221 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 147401448 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 06:04:39 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173424221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1173424221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.4069545374 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 193981370 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069545374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4069545374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.555721211 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2305303761 ps |
| CPU time | 9.34 seconds |
| Started | Oct 09 06:04:39 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555721211 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.555721211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.1517516491 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 144651051 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:41 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517516491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1517516491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.1160521003 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 64777974 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 06:04:38 AM UTC 24 |
| Finished | Oct 09 06:04:40 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160521003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1160521003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.519013282 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 98274526 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519013282 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.519013282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.2385591606 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1271622351 ps |
| CPU time | 5.33 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 244448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385591606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2385591606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2412974853 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 302695392 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412974853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2412974853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.2635800082 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 201574858 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:04:40 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635800082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2635800082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.2292832220 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 933289026 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292832220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2292832220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.748559506 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 105158871 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748559506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.748559506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2643554985 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 118489599 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 06:04:40 AM UTC 24 |
| Finished | Oct 09 06:04:42 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643554985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2643554985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.3917394826 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4466159440 ps |
| CPU time | 15.6 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917394826 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3917394826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.735179862 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 268497327 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735179862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.735179862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.799970824 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 118856742 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:43 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799970824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.799970824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1426993717 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 82665215 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:46 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426993717 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1426993717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.857594074 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2447054634 ps |
| CPU time | 7.51 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 244572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857594074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.857594074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.440673228 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 302776262 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:46 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440673228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.440673228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.3593851233 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 83108291 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593851233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3593851233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.990326633 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 970252665 ps |
| CPU time | 4.56 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:49 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990326633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.990326633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3044357694 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 104024277 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044357694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3044357694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.1280672215 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 120826322 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:41 AM UTC 24 |
| Finished | Oct 09 06:04:44 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280672215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1280672215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.4057216037 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1153784820 ps |
| CPU time | 5.4 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057216037 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4057216037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.873448103 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 368699451 ps |
| CPU time | 2.32 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873448103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.873448103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.2537506058 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 102106582 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 06:04:42 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537506058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2537506058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1482772902 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 87285157 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482772902 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1482772902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.1951615664 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2464096010 ps |
| CPU time | 8 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:54 AM UTC 24 |
| Peak memory | 244548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951615664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1951615664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.173532087 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 302233826 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 239312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173532087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.173532087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.1831911620 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 97859791 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831911620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1831911620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.4245879489 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1442374129 ps |
| CPU time | 5.54 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245879489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4245879489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3283867481 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 150233201 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283867481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3283867481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.1231363950 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 119705111 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:46 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231363950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1231363950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.1416864472 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 12132677013 ps |
| CPU time | 38.51 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:05:25 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416864472 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1416864472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.3645995633 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 468500320 ps |
| CPU time | 2.57 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 220296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645995633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3645995633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.2242636841 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 97998612 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:04:43 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242636841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2242636841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.681139703 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 71744032 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:02 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681139703 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.681139703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3836803449 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2440419955 ps |
| CPU time | 8.22 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:09 AM UTC 24 |
| Peak memory | 243792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836803449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3836803449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2875778046 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 302204543 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:03 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875778046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2875778046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3873024901 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 167400344 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:01 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873024901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3873024901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.132723908 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1693584801 ps |
| CPU time | 6.38 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:06 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132723908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.132723908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.2328123189 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9741530380 ps |
| CPU time | 16.72 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:18 AM UTC 24 |
| Peak memory | 244240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328123189 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2328123189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.630589315 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 143452231 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:02 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630589315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.630589315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.602749952 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 230874827 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 06:03:58 AM UTC 24 |
| Finished | Oct 09 06:04:01 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602749952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.602749952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.3287044574 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1721674313 ps |
| CPU time | 6.81 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:08 AM UTC 24 |
| Peak memory | 227072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287044574 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3287044574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.1750575685 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336402293 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 06:03:59 AM UTC 24 |
| Finished | Oct 09 06:04:02 AM UTC 24 |
| Peak memory | 220076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750575685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1750575685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3572837273 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 113030516 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:03:59 AM UTC 24 |
| Finished | Oct 09 06:04:01 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572837273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3572837273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.923792119 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 85660696 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:49 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923792119 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.923792119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2125447190 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1968677651 ps |
| CPU time | 7.04 seconds |
| Started | Oct 09 06:04:46 AM UTC 24 |
| Finished | Oct 09 06:04:54 AM UTC 24 |
| Peak memory | 243660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125447190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2125447190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4131312699 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 303361661 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 06:04:46 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131312699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4131312699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.1494714033 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 183078779 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:04:45 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494714033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1494714033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.2600406278 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1117917807 ps |
| CPU time | 4.94 seconds |
| Started | Oct 09 06:04:45 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600406278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2600406278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3671044204 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 144485635 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 06:04:46 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671044204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3671044204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.2122193664 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 112653888 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:04:44 AM UTC 24 |
| Finished | Oct 09 06:04:47 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122193664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2122193664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.1729319538 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2407209326 ps |
| CPU time | 10.17 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729319538 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1729319538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.4011316921 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 513579844 ps |
| CPU time | 2.59 seconds |
| Started | Oct 09 06:04:45 AM UTC 24 |
| Finished | Oct 09 06:04:49 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011316921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4011316921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.1018483971 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 113489829 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 06:04:45 AM UTC 24 |
| Finished | Oct 09 06:04:48 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018483971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1018483971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.2358899003 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 91703673 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358899003 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2358899003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2275749088 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1958080342 ps |
| CPU time | 7.1 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 244068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275749088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2275749088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.614417577 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 303025872 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614417577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.614417577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.3598146039 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 103239364 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:49 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598146039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3598146039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.519349821 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 785156655 ps |
| CPU time | 3.64 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519349821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.519349821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1507366668 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 105656434 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507366668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1507366668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3545713983 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 253829361 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545713983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3545713983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.376943362 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4777148650 ps |
| CPU time | 16.2 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376943362 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.376943362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.4015522444 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 371081613 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015522444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4015522444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.3660612881 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 122865788 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 06:04:47 AM UTC 24 |
| Finished | Oct 09 06:04:50 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660612881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3660612881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.1990534451 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 67230367 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990534451 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1990534451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.1523786683 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1269125227 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 244476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523786683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1523786683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3171435815 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 301653274 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171435815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3171435815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.717559284 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 189280326 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717559284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.717559284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.835192033 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1275574095 ps |
| CPU time | 4.91 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835192033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.835192033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2925948701 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 174202148 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925948701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2925948701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.933905397 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 112910060 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933905397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.933905397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.4057712131 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5115203796 ps |
| CPU time | 23.06 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:05:13 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057712131 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4057712131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.131213597 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 289946156 ps |
| CPU time | 2.06 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131213597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.131213597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.3004732344 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 129788425 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004732344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3004732344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.513358894 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 79950602 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513358894 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.513358894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.778309972 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2247599346 ps |
| CPU time | 8.65 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 243724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778309972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.778309972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1943235222 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 301958455 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 239324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943235222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1943235222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.1587552170 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 217443814 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:51 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587552170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1587552170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.337223330 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2186722213 ps |
| CPU time | 7.63 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337223330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.337223330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.164469202 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 183405614 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164469202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.164469202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.4114183561 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 246249587 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114183561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4114183561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.992783444 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1709883345 ps |
| CPU time | 6.72 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992783444 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.992783444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.3835331357 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 146246576 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 06:04:50 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835331357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3835331357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.3293360254 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 209483453 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 06:04:49 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293360254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3293360254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.822044443 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 77898965 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:54 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822044443 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.822044443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.1455226788 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1963834846 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455226788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1455226788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1537589876 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 329241515 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:54 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537589876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1537589876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.4104395208 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 221275841 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 06:04:51 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104395208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4104395208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.1361795094 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1568915175 ps |
| CPU time | 6.1 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361795094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1361795094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.385394978 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 103157879 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385394978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.385394978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.2386637821 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 128288955 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 06:04:51 AM UTC 24 |
| Finished | Oct 09 06:04:53 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386637821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2386637821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1181400032 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 5189328727 ps |
| CPU time | 17.41 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:05:11 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181400032 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1181400032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.743211257 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 264620487 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743211257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.743211257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.3002556081 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 76619112 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:54 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002556081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3002556081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.1433024542 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 71150388 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433024542 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1433024542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.3340996288 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1263800227 ps |
| CPU time | 5.8 seconds |
| Started | Oct 09 06:04:53 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 243656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340996288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3340996288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1068441313 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 302110948 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068441313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1068441313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.1104898563 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 137943418 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104898563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1104898563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.3614809365 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1603885047 ps |
| CPU time | 6.71 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614809365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3614809365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2081017583 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 103445685 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 06:04:53 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081017583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2081017583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3635021191 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 115743512 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 06:04:52 AM UTC 24 |
| Finished | Oct 09 06:04:55 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635021191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3635021191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.3666095714 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2472850147 ps |
| CPU time | 10.17 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666095714 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3666095714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.2044871701 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 393575256 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 06:04:53 AM UTC 24 |
| Finished | Oct 09 06:04:57 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044871701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2044871701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.875755426 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 100450405 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:04:53 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875755426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.875755426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.3363166803 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 78648300 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363166803 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3363166803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.1463282140 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1977336659 ps |
| CPU time | 6.81 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:05:03 AM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463282140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1463282140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3084704395 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 302527854 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084704395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3084704395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.75383097 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 182411913 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75383097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.75383097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1684745417 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1743622070 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:05:01 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684745417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1684745417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4239603867 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 105912097 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239603867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4239603867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.1001840303 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 253625566 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001840303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1001840303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.670980851 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1315170401 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:05:03 AM UTC 24 |
| Peak memory | 220444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670980851 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.670980851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.3939071291 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 289375591 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:57 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939071291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3939071291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3077482550 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 104403446 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:04:54 AM UTC 24 |
| Finished | Oct 09 06:04:56 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077482550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3077482550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.2135268977 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 62745727 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135268977 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2135268977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3181817375 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2252422790 ps |
| CPU time | 7.46 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 244292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181817375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3181817375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3790901249 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 301992890 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790901249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3790901249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.1907292100 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 159566601 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907292100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1907292100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.1955941142 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 708367203 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955941142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1955941142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3843514226 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 100746916 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843514226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3843514226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2963243194 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 115575335 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963243194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2963243194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.1303934233 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3263856888 ps |
| CPU time | 12.86 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:12 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303934233 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1303934233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.1706693454 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 308195564 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:59 AM UTC 24 |
| Peak memory | 220112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706693454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1706693454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.3500842669 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 157194814 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:55 AM UTC 24 |
| Finished | Oct 09 06:04:58 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500842669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3500842669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1895529708 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2447847374 ps |
| CPU time | 7.8 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:17 AM UTC 24 |
| Peak memory | 244524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895529708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1895529708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2727770123 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 301700696 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:01 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727770123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2727770123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.221813931 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 142997659 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:00 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221813931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.221813931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.2467487863 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1403008492 ps |
| CPU time | 5.25 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467487863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2467487863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3258737409 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 168743033 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:01 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258737409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3258737409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.3210671762 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 197535809 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:01 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210671762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3210671762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.1197484162 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 260858188 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 06:04:57 AM UTC 24 |
| Finished | Oct 09 06:05:01 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197484162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1197484162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.2702657236 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 64206410 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 06:05:00 AM UTC 24 |
| Finished | Oct 09 06:05:45 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702657236 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2702657236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.950244895 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 301905374 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:05:00 AM UTC 24 |
| Finished | Oct 09 06:06:06 AM UTC 24 |
| Peak memory | 239336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950244895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.950244895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.2533883524 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4929945278 ps |
| CPU time | 13.93 seconds |
| Started | Oct 09 06:05:00 AM UTC 24 |
| Finished | Oct 09 06:06:08 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533883524 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2533883524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.30084728 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 62743455 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30084728 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.30084728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.2160182541 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2452919863 ps |
| CPU time | 8.63 seconds |
| Started | Oct 09 06:04:01 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 243800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160182541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2160182541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2096599640 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 302160278 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:04:02 AM UTC 24 |
| Finished | Oct 09 06:04:04 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096599640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2096599640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.1788249997 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 181371905 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:02 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788249997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1788249997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3889544932 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 780127472 ps |
| CPU time | 4.38 seconds |
| Started | Oct 09 06:04:01 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889544932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3889544932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3594359560 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 17676138253 ps |
| CPU time | 28.89 seconds |
| Started | Oct 09 06:04:02 AM UTC 24 |
| Finished | Oct 09 06:04:32 AM UTC 24 |
| Peak memory | 244392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594359560 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3594359560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3068817637 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 176526861 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 06:04:01 AM UTC 24 |
| Finished | Oct 09 06:04:04 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068817637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3068817637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.113406480 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 120746701 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 06:04:00 AM UTC 24 |
| Finished | Oct 09 06:04:02 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113406480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.113406480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1306213156 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1751968131 ps |
| CPU time | 7.88 seconds |
| Started | Oct 09 06:04:02 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306213156 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1306213156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.37198878 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 139196069 ps |
| CPU time | 2.15 seconds |
| Started | Oct 09 06:04:01 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37198878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.37198878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.634854902 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 63980672 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:04:01 AM UTC 24 |
| Finished | Oct 09 06:04:03 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634854902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.634854902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.676394979 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1274157182 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 06:05:01 AM UTC 24 |
| Finished | Oct 09 06:05:25 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676394979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.676394979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1769663375 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 137573203 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 06:05:00 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769663375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1769663375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.4199794454 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 109278714 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:05:00 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199794454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4199794454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.3809121862 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 60362150 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 06:05:04 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809121862 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3809121862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.100100553 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2454934871 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 06:05:03 AM UTC 24 |
| Finished | Oct 09 06:05:33 AM UTC 24 |
| Peak memory | 243648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100100553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.100100553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.85311364 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 301375966 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:05:03 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85311364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.85311364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.776281140 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5446789360 ps |
| CPU time | 16.97 seconds |
| Started | Oct 09 06:05:03 AM UTC 24 |
| Finished | Oct 09 06:05:42 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776281140 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.776281140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.2767252807 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 67440718 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 06:05:08 AM UTC 24 |
| Finished | Oct 09 06:05:10 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767252807 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2767252807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.3791486676 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1975468615 ps |
| CPU time | 6.49 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:31 AM UTC 24 |
| Peak memory | 244124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791486676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3791486676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.289683627 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 302322110 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289683627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.289683627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.2563757598 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 158280257 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:15 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563757598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2563757598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.1918084558 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1463960083 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:19 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918084558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1918084558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1146415790 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 107658086 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:15 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146415790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1146415790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.1792669020 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 203867713 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 06:05:04 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792669020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1792669020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.3770607503 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 166499384 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:25 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770607503 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3770607503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.749718789 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 314781024 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749718789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.749718789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.3080292014 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 86652821 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 06:05:06 AM UTC 24 |
| Finished | Oct 09 06:05:15 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080292014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3080292014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.2413154789 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 201776488 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 06:05:10 AM UTC 24 |
| Finished | Oct 09 06:06:12 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413154789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2413154789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1367816927 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 904069696 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 06:05:11 AM UTC 24 |
| Finished | Oct 09 06:05:29 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367816927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1367816927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.181740383 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 181111805 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 06:05:14 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181740383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.181740383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.3310211651 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 126318029 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 06:05:09 AM UTC 24 |
| Finished | Oct 09 06:06:02 AM UTC 24 |
| Peak memory | 210224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310211651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3310211651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.261398404 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 120038428 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 06:05:13 AM UTC 24 |
| Finished | Oct 09 06:05:26 AM UTC 24 |
| Peak memory | 219500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261398404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.261398404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.3454677818 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 69491980 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 06:05:26 AM UTC 24 |
| Finished | Oct 09 06:05:35 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454677818 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3454677818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.3542770192 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1972804882 ps |
| CPU time | 6.34 seconds |
| Started | Oct 09 06:05:25 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 243552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542770192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3542770192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4224872786 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 301245182 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 06:05:25 AM UTC 24 |
| Finished | Oct 09 06:05:30 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224872786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4224872786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.6135220 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 172784288 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 06:05:20 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6135220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.6135220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.1967443960 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1299214575 ps |
| CPU time | 4.34 seconds |
| Started | Oct 09 06:05:20 AM UTC 24 |
| Finished | Oct 09 06:05:59 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967443960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1967443960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3955218476 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 143284894 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:05:25 AM UTC 24 |
| Finished | Oct 09 06:05:30 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955218476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3955218476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.3817206834 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3155722512 ps |
| CPU time | 10.3 seconds |
| Started | Oct 09 06:05:26 AM UTC 24 |
| Finished | Oct 09 06:05:45 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817206834 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3817206834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.3897746276 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 452566534 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:05:25 AM UTC 24 |
| Finished | Oct 09 06:05:32 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897746276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3897746276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.3951062205 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 138915212 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:05:21 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951062205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3951062205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.2647773743 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 64828932 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 06:05:30 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647773743 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2647773743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.3469262627 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1947673657 ps |
| CPU time | 7.1 seconds |
| Started | Oct 09 06:05:28 AM UTC 24 |
| Finished | Oct 09 06:05:37 AM UTC 24 |
| Peak memory | 243980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469262627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3469262627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1925665506 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 301610527 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 06:05:30 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925665506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1925665506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.1585122646 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 100813610 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 06:05:27 AM UTC 24 |
| Finished | Oct 09 06:05:35 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585122646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1585122646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.220480800 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 987446640 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 06:05:27 AM UTC 24 |
| Finished | Oct 09 06:05:39 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220480800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.220480800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1740261642 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 144446149 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 06:05:28 AM UTC 24 |
| Finished | Oct 09 06:05:31 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740261642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1740261642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.1191496727 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 194583042 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:05:26 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191496727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1191496727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.1613627923 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1638376013 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 06:05:30 AM UTC 24 |
| Finished | Oct 09 06:06:10 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613627923 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1613627923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3671813693 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 311365240 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 06:05:28 AM UTC 24 |
| Finished | Oct 09 06:05:32 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671813693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3671813693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.3174683568 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 237167123 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 06:05:27 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174683568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3174683568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.464147599 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 60121378 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 06:05:36 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464147599 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.464147599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.732873822 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1281783670 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 06:05:32 AM UTC 24 |
| Finished | Oct 09 06:05:41 AM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732873822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.732873822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2457223778 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 302738532 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 06:05:33 AM UTC 24 |
| Finished | Oct 09 06:05:35 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457223778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2457223778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2753900897 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 99783747 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 06:05:31 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753900897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2753900897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2923666953 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 735946797 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 06:05:31 AM UTC 24 |
| Finished | Oct 09 06:05:38 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923666953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2923666953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1574693951 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 145939392 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 06:05:32 AM UTC 24 |
| Finished | Oct 09 06:05:37 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574693951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1574693951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.514977998 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 183235127 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 06:05:31 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514977998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.514977998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.170489380 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 310481635 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 06:05:32 AM UTC 24 |
| Finished | Oct 09 06:05:41 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170489380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.170489380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.2880188097 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 201443286 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 06:05:31 AM UTC 24 |
| Finished | Oct 09 06:05:36 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880188097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2880188097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.2685576586 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 75330224 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:05:40 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685576586 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2685576586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3892919826 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1968995096 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:05:47 AM UTC 24 |
| Peak memory | 244008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892919826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3892919826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2675192232 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 302284008 ps |
| CPU time | 1 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:05:41 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675192232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2675192232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.1278533283 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 211493683 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 06:05:36 AM UTC 24 |
| Finished | Oct 09 06:05:45 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278533283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1278533283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.2406792687 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1072293888 ps |
| CPU time | 4.39 seconds |
| Started | Oct 09 06:05:36 AM UTC 24 |
| Finished | Oct 09 06:05:49 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406792687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2406792687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.524988475 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 111034082 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:05:41 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524988475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.524988475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.4189091714 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 258652211 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 06:05:36 AM UTC 24 |
| Finished | Oct 09 06:05:56 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189091714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4189091714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3125345404 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5980832748 ps |
| CPU time | 19.7 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125345404 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3125345404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.3058582703 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 322293256 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 06:05:38 AM UTC 24 |
| Finished | Oct 09 06:05:42 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058582703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3058582703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.982832819 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 179786403 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 06:05:36 AM UTC 24 |
| Finished | Oct 09 06:05:56 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982832819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.982832819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2483266936 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 73619018 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:50 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483266936 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2483266936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.299477890 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2256805936 ps |
| CPU time | 7.32 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:06:03 AM UTC 24 |
| Peak memory | 243724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299477890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.299477890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1500469283 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 301577474 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:06:00 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500469283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1500469283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.3384249560 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 124989879 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 06:05:40 AM UTC 24 |
| Finished | Oct 09 06:06:05 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384249560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3384249560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.3640987343 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 197650969 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 06:05:39 AM UTC 24 |
| Finished | Oct 09 06:05:41 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640987343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3640987343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.1257574877 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 9605154621 ps |
| CPU time | 28.74 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:06:18 AM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257574877 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1257574877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.3952214638 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 254734253 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:57 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952214638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3952214638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3614806495 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 263321032 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:56 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614806495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3614806495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.1459186240 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 82313215 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 06:05:42 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459186240 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1459186240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.61567088 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1269380942 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 06:05:42 AM UTC 24 |
| Finished | Oct 09 06:05:49 AM UTC 24 |
| Peak memory | 244232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61567088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.61567088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.70291769 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 303610535 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 06:05:42 AM UTC 24 |
| Finished | Oct 09 06:05:45 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70291769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.70291769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.561118913 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 178492823 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:50 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561118913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.561118913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.3362366491 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1516211502 ps |
| CPU time | 5.67 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362366491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3362366491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2128086610 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 99607334 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:50 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128086610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2128086610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.2006897972 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 116070006 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:50 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006897972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2006897972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1230960639 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 6095114801 ps |
| CPU time | 23.12 seconds |
| Started | Oct 09 06:05:42 AM UTC 24 |
| Finished | Oct 09 06:06:08 AM UTC 24 |
| Peak memory | 222576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230960639 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1230960639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.2131185433 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 143693875 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:51 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131185433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2131185433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.2559614058 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 148022719 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 06:05:41 AM UTC 24 |
| Finished | Oct 09 06:05:50 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559614058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2559614058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.3281147370 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 66155428 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 06:04:04 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281147370 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3281147370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1826484723 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 300865491 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 06:04:04 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826484723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1826484723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.4269692149 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 73823388 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269692149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4269692149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1846890231 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1575243758 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846890231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1846890231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3601728780 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 170946906 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:06 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601728780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3601728780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3272042143 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 211242339 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272042143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3272042143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3525211490 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3397549785 ps |
| CPU time | 14.65 seconds |
| Started | Oct 09 06:04:04 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525211490 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3525211490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1161547721 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 357292613 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161547721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1161547721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1455376344 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 166949825 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 06:04:03 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455376344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1455376344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1169968838 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 54771725 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:08 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169968838 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1169968838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2904757281 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1272617671 ps |
| CPU time | 5.96 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 244468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904757281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2904757281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1562207050 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 308625711 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:08 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562207050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1562207050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1026521262 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 184000347 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 06:04:05 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026521262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1026521262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2210137018 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 776707913 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 06:04:05 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210137018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2210137018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.430733308 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 98913100 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:08 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430733308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.430733308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2640265692 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 128153737 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 06:04:04 AM UTC 24 |
| Finished | Oct 09 06:04:07 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640265692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2640265692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.2817395413 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 5035569083 ps |
| CPU time | 16.75 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:24 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817395413 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2817395413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.950452547 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 265485393 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:09 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950452547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.950452547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2297691724 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 72109176 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:08 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297691724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2297691724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2090656895 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 71701073 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 06:04:08 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090656895 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2090656895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.1245919803 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2448047916 ps |
| CPU time | 8.93 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:18 AM UTC 24 |
| Peak memory | 244516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245919803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1245919803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.867216351 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 301833592 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867216351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.867216351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.553258031 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 138996389 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:09 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553258031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.553258031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3496102788 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 904201470 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496102788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3496102788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.679969522 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 145244196 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679969522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.679969522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2009564286 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 197111353 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 06:04:06 AM UTC 24 |
| Finished | Oct 09 06:04:09 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009564286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2009564286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.2549046372 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 10571201701 ps |
| CPU time | 33.64 seconds |
| Started | Oct 09 06:04:08 AM UTC 24 |
| Finished | Oct 09 06:04:43 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549046372 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2549046372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.207061441 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 545532012 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:12 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207061441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.207061441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2013449108 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 237775819 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 06:04:07 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 210224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013449108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2013449108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3768293013 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 97492217 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:12 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768293013 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3768293013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1063575147 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1268657807 ps |
| CPU time | 5.93 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 243764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063575147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1063575147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1615334487 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 301874195 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 239328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615334487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1615334487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2008254576 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 138778799 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008254576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2008254576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1631799147 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1440831380 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631799147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1631799147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1686188869 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 145791655 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:12 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686188869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1686188869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3646686729 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 203064150 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 06:04:08 AM UTC 24 |
| Finished | Oct 09 06:04:10 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646686729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3646686729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1117758308 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 10875206532 ps |
| CPU time | 33.83 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117758308 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1117758308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3545263957 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 151077705 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:12 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545263957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3545263957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.2891990754 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 97705686 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 06:04:09 AM UTC 24 |
| Finished | Oct 09 06:04:11 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891990754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2891990754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3237616848 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 69163328 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:14 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237616848 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3237616848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3657297881 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1272125555 ps |
| CPU time | 6.04 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657297881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3657297881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.208259481 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 302242787 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:15 AM UTC 24 |
| Peak memory | 239332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208259481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.208259481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3253926957 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 153984445 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253926957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3253926957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3178963521 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 960779411 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:16 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178963521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3178963521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4208997591 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 101362794 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:14 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208997591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4208997591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.469845273 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 196939297 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 06:04:10 AM UTC 24 |
| Finished | Oct 09 06:04:13 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469845273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.469845273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.3609582283 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15837981186 ps |
| CPU time | 53.72 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:05:07 AM UTC 24 |
| Peak memory | 220396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609582283 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3609582283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4178650874 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 105612854 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 06:04:12 AM UTC 24 |
| Finished | Oct 09 06:04:14 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178650874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4178650874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |