Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8566

1

T4

7

T9

6

T12

25

auto[1]

11243

1

T2

4

T3

4

T4

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6146	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6627	1			T1	1		T2	2		T3	2
reset_info_cp[2]	3041	1			T2	1		T3	1		T10	1
reset_info_cp[4]	4045	1			T2	1		T3	1		T10	1
reset_info_cp[8]	93	1			T61	1		T72	1		T57	1
reset_info_cp[16]	106	1			T9	1		T24	1		T61	1
reset_info_cp[32]	101	1			T9	1		T62	1		T43	1
reset_info_cp[64]	128	1			T4	1		T23	1		T56	1
reset_info_cp[128]	131	1			T61	1		T72	1		T94	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3251	1			T12	4		T61	20		T92	10
reset_info_cp[1]	auto[1]	2767	1			T2	1		T3	1		T10	1
reset_info_cp[2]	auto[0]	968	1			T12	5		T92	4		T56	6
reset_info_cp[2]	auto[1]	2073	1			T2	1		T3	1		T10	1
reset_info_cp[4]	auto[0]	1500	1			T12	3		T92	8		T56	8
reset_info_cp[4]	auto[1]	2545	1			T2	1		T3	1		T10	1
reset_info_cp[8]	auto[0]	35	1			T72	1		T57	1		T89	2
reset_info_cp[8]	auto[1]	58	1			T61	1		T44	2		T91	1
reset_info_cp[16]	auto[0]	38	1			T9	1		T72	1		T56	1
reset_info_cp[16]	auto[1]	68	1			T24	1		T61	1		T59	1
reset_info_cp[32]	auto[0]	48	1			T9	1		T40	1		T161	1
reset_info_cp[32]	auto[1]	53	1			T62	1		T43	1		T44	1
reset_info_cp[64]	auto[0]	46	1			T4	1		T107	1		T110	1
reset_info_cp[64]	auto[1]	82	1			T23	1		T56	1		T59	1
reset_info_cp[128]	auto[0]	54	1			T72	1		T94	1		T160	2
reset_info_cp[128]	auto[1]	77	1			T61	1		T62	1		T25	3