---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A	0	0	1640650	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A	0	0	54106492	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A	0	0	12985223	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A	0	0	51940267	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	11439832	6492483	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	11439832	80	0	0
tb.dut.ParameterMatch_A	0	0	494	494	0	0
tb.dut.PwrKnownO_A	0	0	11439832	6492483	0	0
tb.dut.ResetsKnownO_A	0	0	11439832	6492483	0	0
tb.dut.RstEnKnownO_A	0	0	11439832	6492483	0	0
tb.dut.TlAReadyKnownO_A	0	0	11439832	6492483	0	0
tb.dut.TlDValidKnownO_A	0	0	11439832	6492483	0	0
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	0	0	11439832	80	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A	0	0	1640650	977626	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0	0	0	9505	9011	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0	0	0	7203	6709	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A	0	0	1640650	958697	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	11439832	13443	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	11439832	123747	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	11439832	6533747	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	11439832	197485	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	11439832	13443	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	11439832	123747	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	11439832	6533747	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	11439832	197485	0	0
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A	0	0	494	494	0	0
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A	0	0	494	494	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A	0	0	54106492	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A	0	0	54106492	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A	0	0	51940267	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A	0	0	51940267	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A	0	0	25971125	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A	0	0	25971125	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A	0	0	12985223	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A	0	0	12985223	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A	0	0	25971343	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A	0	0	25971343	9070	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A	0	0	1640650	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A	0	0	1640650	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A	0	0	1640650	7218	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A	0	0	1640650	251	0	0
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A	0	0	1640650	9070	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	0	0	12985223	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	0	0	12985223	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A	0	0	11439832	22513	0	0
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A	0	0	12194319	7331	0	0
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A	0	0	12194319	5935	0	0
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A	0	0	12194319	5836	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A	0	0	12194319	8805	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A	0	0	12194319	8848	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A	0	0	12194319	8760	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A	0	0	12194319	8785	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A	0	0	12194319	8916	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A	0	0	12194319	8640	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A	0	0	12194319	8573	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A	0	0	12194319	8913	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A	0	0	12194319	6014	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A	0	0	12194319	6004	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A	0	0	12194319	6214	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A	0	0	12194319	6018	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A	0	0	12194319	6141	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A	0	0	12194319	5955	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A	0	0	12194319	6120	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A	0	0	12194319	6101	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A	0	0	12985223	14598	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A	0	0	12985223	23564	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A	0	0	12985223	14654	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A	0	0	12985223	23613	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A	0	0	12985223	14711	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A	0	0	12985223	23678	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25971125	13518	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25971125	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12985223	13542	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12985223	22562	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A	0	0	51940267	13519	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A	0	0	51940267	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A	0	0	54106492	13564	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	54106492	22562	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A	0	0	25971343	13510	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A	0	0	25971343	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A	0	0	1640650	50	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A	0	0	1640650	9051	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A	0	0	12985223	14359	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A	0	0	12985223	23322	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A	0	0	51940267	14399	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A	0	0	51940267	23364	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A	0	0	25971125	14453	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A	0	0	25971125	23408	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A	0	0	54106492	13524	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A	0	0	54106492	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A	0	0	1640650	13861	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A	0	0	1640650	22324	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A	0	0	25971343	14508	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A	0	0	25971343	23470	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A	0	0	1640650	13465	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A	0	0	1640650	22494	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25971125	13462	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25971125	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12985223	13492	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12985223	22562	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A	0	0	51940267	13469	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A	0	0	51940267	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A	0	0	54106492	13515	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	54106492	22562	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A	0	0	25971343	13468	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A	0	0	25971343	22513	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A	0	0	1640650	9070	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A	0	0	54106492	21	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A	0	0	25971125	19	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A	0	0	25971125	2326	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A	0	0	12985223	9070	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A	0	0	51940267	21	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A	0	0	25971343	28	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A	0	0	25971343	2326	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A	0	0	12985223	13467	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A	0	0	12985223	22513	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A	0	0	12985223	14250	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A	0	0	12985223	1009	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A	0	0	12985223	14250	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A	0	0	12985223	1009	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A	0	0	51940267	13037	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A	0	0	51940267	949	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A	0	0	51940267	13037	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A	0	0	51940267	949	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A	0	0	25971125	13083	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A	0	0	25971125	942	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A	0	0	25971125	13083	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A	0	0	25971125	942	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A	0	0	25971343	13145	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A	0	0	25971343	987	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A	0	0	25971343	13145	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A	0	0	25971343	987	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A	0	0	1640650	21944	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A	0	0	1640650	1023	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A	0	0	1640650	21944	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A	0	0	1640650	1023	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A	0	0	12985223	14492	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A	0	0	12985223	1083	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOff_A	0	0	12985223	14492	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A	0	0	12985223	1083	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOff_A	0	0	12985223	14542	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A	0	0	12985223	1135	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOff_A	0	0	12985223	14542	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A	0	0	12985223	1135	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A	0	0	12985223	14607	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A	0	0	12985223	1195	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOff_A	0	0	12985223	14607	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A	0	0	12985223	1195	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	12194319	1140836	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	12194319	6977875	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	12194319	6977875	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	12194319	2034157	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	12194319	6977875	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	12194319	6977875	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
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tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
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tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
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tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
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tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	609	609	0	0
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tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	12194928	501609	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	12194319	5345	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	12194928	846102	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	12194928	1053671	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	12194319	5736	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	12194928	1141006	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	12194928	2034330	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	12194928	1141006	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	12194928	2034330	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	12194928	2034330	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	12194928	2034330	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	12194319	3170	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	12194319	2526	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	609	609	0	0
tb.dut.u_alert_info.CntStoreSlot_A	0	0	494	494	0	0
tb.dut.u_alert_info.CntWidth_A	0	0	494	494	0	0
tb.dut.u_cpu_info.CntStoreSlot_A	0	0	494	494	0	0
tb.dut.u_cpu_info.CntWidth_A	0	0	494	494	0	0
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A	0	0	12985223	7655887	0	0
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	12985223	7655887	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6406814	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23562	23068	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
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tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
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tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6404626	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23612	23118	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
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tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
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tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6410809	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23677	23183	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
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tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	27327225	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	51940267	26234129	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971125	13106738	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6525386	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6525386	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	27327421	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971343	13107008	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6394084	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23320	22826	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A	0	0	51940267	25719776	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23359	22865	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971125	12851035	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23405	22911	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	27021621	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971343	12862388	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23467	22973	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22445	21951	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1640650	795221	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23483	22989	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	28070205	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22445	21951	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1640650	832590	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	51940267	26947434	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971125	13463526	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
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tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6703702	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6703702	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	28070315	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971343	13463462	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A	0	0	54106492	31921346	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	51940267	30643098	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971125	15317906	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	7655887	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25971343	15317699	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	9070	8576	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22562	22068	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12985223	6630128	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	494	494	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11439832	6492483	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11439832	6492483	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_reg.en2addrHit	0	0	12194319	992250	0	0
tb.dut.u_reg.reAfterRv	0	0	12194319	992102	0	0
tb.dut.u_reg.rePulse	0	0	12194319	531604	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	609	609	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	609	609	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	609	609	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	609	609	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	609	609	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	609	609	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	609	609	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	609	609	0	0
tb.dut.u_reg.wePulse	0	0	12194319	460498	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	22513	22019	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2840	2346	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	12194928	6579	6579	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	12194928	2686	2686	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	12194928	2693	2693	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	12194928	1890	1890	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	12194928	119	119	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	12194928	1453	1453	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	12194928	1248	1248	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	12194928	3041	3041	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	12194928	53837	53837	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	12194928	461574	461574	447

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	12194928	6579	6579	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	12194928	2686	2686	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	12194928	2693	2693	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	12194928	1890	1890	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	12194928	119	119	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	12194928	1453	1453	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	12194928	1248	1248	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	12194928	3041	3041	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	12194928	53837	53837	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	12194928	461574	461574	447