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LINE 1358
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T80,T81,T83 |
| 1 | 1 | 1 | Covered | T2,T4,T6 |
LINE 1361
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T80,T82,T84 |
| 1 | 1 | 1 | Covered | T2,T4,T6 |
LINE 1364
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T80,T99,T84 |
| 1 | 1 | 1 | Covered | T2,T4,T6 |