| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T81 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1410098547 | Oct 12 12:04:59 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 143831675 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.318247690 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 96238084 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.357668961 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 81189793 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2892760831 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 66321547 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.4147769590 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 78735631 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1359059709 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 117818729 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3089025369 | Oct 12 12:04:59 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 882339409 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2050907268 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 145819788 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2057599803 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:03 AM UTC 24 | 142156951 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.898918991 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 103238677 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4053604469 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 206859492 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3518274503 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 210404736 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2177401326 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 70448634 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4022802483 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 210069062 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1254905571 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 465360061 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3708925607 | Oct 12 12:05:02 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 127698482 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.4272194959 | Oct 12 12:05:02 AM UTC 24 | Oct 12 12:05:04 AM UTC 24 | 77399587 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.30186260 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 297274825 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3715326136 | Oct 12 12:05:03 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 117819508 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3246986466 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 896988086 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.461225778 | Oct 12 12:05:03 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 108439038 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3375711051 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 276458788 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2275594156 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:05 AM UTC 24 | 459400107 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2256367059 | Oct 12 12:05:02 AM UTC 24 | Oct 12 12:05:06 AM UTC 24 | 236035611 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1733922165 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:06 AM UTC 24 | 60857062 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.941484311 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:06 AM UTC 24 | 128082457 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.475571799 | Oct 12 12:05:02 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 925457661 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.365184605 | Oct 12 12:05:05 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 67162006 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2055828472 | Oct 12 12:05:05 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 125319482 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4145175029 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 124067285 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4015180148 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 487819514 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1128562651 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:07 AM UTC 24 | 209580952 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1125205355 | Oct 12 12:05:05 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 271997407 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.962522302 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 248189627 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1012511228 | Oct 12 12:05:05 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 425027454 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.3212431402 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 72106843 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.4171794184 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 60953720 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1644146797 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:08 AM UTC 24 | 104652982 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1436306406 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:09 AM UTC 24 | 172774200 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2650377780 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:09 AM UTC 24 | 223449659 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1828329804 | Oct 12 12:05:04 AM UTC 24 | Oct 12 12:05:09 AM UTC 24 | 279487140 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.884567967 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:09 AM UTC 24 | 425442105 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1347676580 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 482455403 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3903342093 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:09 AM UTC 24 | 124116171 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3030294501 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 116360863 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3977558395 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 238116560 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3386712221 | Oct 12 12:05:08 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 77028478 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1518819058 | Oct 12 12:05:08 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 117654110 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1176001468 | Oct 12 12:05:07 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 145153476 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3953490504 | Oct 12 12:05:08 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 156832125 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3270923955 | Oct 12 12:05:02 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 477653730 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3019216559 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:10 AM UTC 24 | 436198416 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1860750681 | Oct 12 12:05:07 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 221659540 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1086237053 | Oct 12 12:05:06 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 874614510 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.4239962129 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 61077316 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2981396507 | Oct 12 12:05:01 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 2296683519 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.426513231 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 60191665 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.554468780 | Oct 12 12:04:59 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 2315141403 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2553569814 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 154452932 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2433586189 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:11 AM UTC 24 | 215031078 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1142079025 | Oct 12 12:05:08 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 763736662 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.4052356537 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 119246306 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1952946727 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 75861735 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1367886468 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 79024487 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1885730671 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 146192842 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.3905714542 | Oct 12 12:05:11 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 63022652 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2054609049 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 332148958 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2425758926 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:12 AM UTC 24 | 136863838 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1786696585 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:13 AM UTC 24 | 116818921 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1729666184 | Oct 12 12:05:09 AM UTC 24 | Oct 12 12:05:13 AM UTC 24 | 889088859 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.674603902 | Oct 12 12:05:11 AM UTC 24 | Oct 12 12:05:13 AM UTC 24 | 233982751 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2478854217 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:13 AM UTC 24 | 428025748 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2548953164 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:13 AM UTC 24 | 507954770 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3279151149 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 66027979 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.184937152 | Oct 12 12:05:10 AM UTC 24 | Oct 12 12:05:14 AM UTC 24 | 186373490 ps | ||
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| T578 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1271080102 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 114862322 ps | ||
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| T580 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3912271451 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 132731603 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1938861962 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 126247804 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2925076946 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:15 AM UTC 24 | 92275472 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.395219331 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 132154830 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2301513622 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 79987716 ps | ||
| T585 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2571342821 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 87147917 ps | ||
| T586 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2100550176 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 113525516 ps | ||
| T587 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3284928004 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 196273139 ps | ||
| T588 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1981401812 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 412108456 ps | ||
| T589 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.3268586018 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 86994077 ps | ||
| T590 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.268767795 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 110236163 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1601161544 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:16 AM UTC 24 | 439622871 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3495991489 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 429206377 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2694974368 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 421528598 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3741486036 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 929782588 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2253385681 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 319780591 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3927503449 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 202447380 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1256569222 | Oct 12 12:05:15 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 92788654 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.419438939 | Oct 12 12:05:15 AM UTC 24 | Oct 12 12:05:17 AM UTC 24 | 91664327 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1489312888 | Oct 12 12:05:15 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 57235405 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3461531177 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 108233768 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.4147457134 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 66531190 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3304685379 | Oct 12 12:05:14 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 776208627 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.744111304 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 261244904 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.4101081241 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:18 AM UTC 24 | 120650618 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1569857408 | Oct 12 12:05:15 AM UTC 24 | Oct 12 12:05:19 AM UTC 24 | 473028592 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1157259250 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:19 AM UTC 24 | 201247204 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.385507725 | Oct 12 12:05:13 AM UTC 24 | Oct 12 12:05:19 AM UTC 24 | 637126494 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.3311167386 | Oct 12 12:05:15 AM UTC 24 | Oct 12 12:05:19 AM UTC 24 | 153107007 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1869777694 | Oct 12 12:05:17 AM UTC 24 | Oct 12 12:05:19 AM UTC 24 | 136362922 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4033832332 | Oct 12 12:05:16 AM UTC 24 | Oct 12 12:05:20 AM UTC 24 | 874781450 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.3667516335 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 119525728 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667516335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3667516335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2811042578 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 483243504 ps |
| CPU time | 3.17 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811042578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2811042578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.256288674 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2487666090 ps |
| CPU time | 8.61 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256288674 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.256288674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1074562215 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 106605288 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:01 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1074562215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w ith_rand_reset.1074562215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2938226538 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1277461203 ps |
| CPU time | 6.93 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:37 AM UTC 24 |
| Peak memory | 243772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938226538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2938226538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3075590626 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8500816743 ps |
| CPU time | 13.46 seconds |
| Started | Oct 12 12:50:32 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 244108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075590626 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3075590626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3246986466 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 896988086 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246986466 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.3246986466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.532001579 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1266578812 ps |
| CPU time | 5.68 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 244132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532001579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.532001579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.263494963 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 61655359 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:50:32 AM UTC 24 |
| Finished | Oct 12 12:50:34 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263494963 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.263494963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3857993049 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 254326362 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:03 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857993049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3857993049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2275594156 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 459400107 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275594156 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2275594156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3122513125 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 111871516 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:31 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122513125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3122513125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.967808951 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 279283688 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967808951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.967808951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3887107519 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 499581446 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:14 AM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887107519 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3887107519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3551365066 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 59373569 ps |
| CPU time | 0.81 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:01 AM UTC 24 |
| Peak memory | 207852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551365066 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3551365066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3164011569 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 156246617 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164011569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3164011569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1672349740 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4938993874 ps |
| CPU time | 24.95 seconds |
| Started | Oct 12 12:50:32 AM UTC 24 |
| Finished | Oct 12 12:50:59 AM UTC 24 |
| Peak memory | 220092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672349740 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1672349740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3741486036 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 929782588 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741486036 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3741486036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2955330315 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1269127759 ps |
| CPU time | 7.21 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 244088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955330315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2955330315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.475571799 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 925457661 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 12:05:02 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475571799 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.475571799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.107605113 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 104116015 ps |
| CPU time | 1.34 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:01 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107605113 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.107605113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.554468780 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2315141403 ps |
| CPU time | 10.91 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554468780 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.554468780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2427214980 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 137855329 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:01 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427214980 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2427214980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3709630755 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 147982986 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:01 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709630755 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.3709630755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.1275793178 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 120956052 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:02 AM UTC 24 |
| Peak memory | 217488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275793178 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1275793178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3089025369 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 882339409 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089025369 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.3089025369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3518274503 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 210404736 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518274503 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3518274503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2981396507 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2296683519 ps |
| CPU time | 9.12 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 209020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981396507 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2981396507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.318247690 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 96238084 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318247690 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.318247690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4053604469 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 206859492 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 221440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4053604469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.4053604469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.357668961 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 81189793 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357668961 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.357668961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1359059709 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 117818729 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359059709 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.1359059709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1410098547 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 143831675 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 12:04:59 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410098547 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1410098547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1885730671 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 146192842 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1885730671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1885730671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.426513231 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 60191665 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426513231 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.426513231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1367886468 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 79024487 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367886468 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1367886468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2054609049 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 332148958 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054609049 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2054609049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1729666184 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 889088859 ps |
| CPU time | 2.91 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:13 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729666184 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1729666184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1786696585 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 116818921 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:13 AM UTC 24 |
| Peak memory | 207896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1786696585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.1786696585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1952946727 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 75861735 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952946727 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1952946727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2425758926 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 136863838 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425758926 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.2425758926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2478854217 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 428025748 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:13 AM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478854217 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.2478854217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1271080102 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 114862322 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1271080102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.1271080102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.3905714542 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 63022652 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 12:05:11 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905714542 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3905714542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.674603902 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 233982751 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:05:11 AM UTC 24 |
| Finished | Oct 12 12:05:13 AM UTC 24 |
| Peak memory | 217344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674603902 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.674603902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.184937152 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 186373490 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:14 AM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184937152 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.184937152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2548953164 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 507954770 ps |
| CPU time | 1.9 seconds |
| Started | Oct 12 12:05:10 AM UTC 24 |
| Finished | Oct 12 12:05:13 AM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548953164 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.2548953164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3718486158 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 91408832 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3718486158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.3718486158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2892760831 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 66321547 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892760831 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2892760831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3912271451 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 132731603 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912271451 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.3912271451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2694974368 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 421528598 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694974368 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2694974368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3284928004 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 196273139 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3284928004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.3284928004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2177401326 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 70448634 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177401326 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2177401326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1938861962 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 126247804 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938861962 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.1938861962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2925076946 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 92275472 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:15 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925076946 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2925076946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1981401812 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 412108456 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981401812 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1981401812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.395219331 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 132154830 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=395219331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_w ith_rand_reset.395219331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2571342821 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 87147917 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571342821 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2571342821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2100550176 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 113525516 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100550176 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.2100550176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.3927503449 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 202447380 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927503449 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3927503449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3495991489 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 429206377 ps |
| CPU time | 2.24 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495991489 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3495991489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.268767795 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 110236163 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=268767795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_w ith_rand_reset.268767795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.3268586018 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 86994077 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268586018 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3268586018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2301513622 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 79987716 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301513622 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.2301513622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.385507725 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 637126494 ps |
| CPU time | 4.23 seconds |
| Started | Oct 12 12:05:13 AM UTC 24 |
| Finished | Oct 12 12:05:19 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385507725 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.385507725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1601161544 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 439622871 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601161544 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.1601161544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1256569222 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 92788654 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:05:15 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1256569222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.1256569222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3279151149 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 66027979 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:16 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279151149 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3279151149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.419438939 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 91664327 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:05:15 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419438939 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.419438939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2253385681 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 319780591 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:17 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253385681 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2253385681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3304685379 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 776208627 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 12:05:14 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304685379 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.3304685379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3461531177 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 108233768 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3461531177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.3461531177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1489312888 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 57235405 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:05:15 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489312888 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1489312888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.744111304 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 261244904 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744111304 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.744111304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.3311167386 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 153107007 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 12:05:15 AM UTC 24 |
| Finished | Oct 12 12:05:19 AM UTC 24 |
| Peak memory | 221900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311167386 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3311167386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1569857408 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 473028592 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 12:05:15 AM UTC 24 |
| Finished | Oct 12 12:05:19 AM UTC 24 |
| Peak memory | 209128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569857408 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.1569857408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1869777694 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 136362922 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 12:05:17 AM UTC 24 |
| Finished | Oct 12 12:05:19 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1869777694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.1869777694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.4147457134 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 66531190 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147457134 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4147457134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1157259250 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 201247204 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:19 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157259250 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.1157259250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.4101081241 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 120650618 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:18 AM UTC 24 |
| Peak memory | 225212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101081241 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4101081241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4033832332 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 874781450 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 12:05:16 AM UTC 24 |
| Finished | Oct 12 12:05:20 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033832332 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.4033832332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.898918991 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 103238677 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 207924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898918991 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.898918991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3375711051 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 276458788 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375711051 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3375711051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2050907268 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 145819788 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050907268 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2050907268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2057599803 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 142156951 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2057599803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2057599803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.4147769590 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 78735631 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:03 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147769590 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4147769590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4022802483 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 210069062 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022802483 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.4022802483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1254905571 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 465360061 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254905571 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.1254905571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2256367059 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 236035611 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 12:05:02 AM UTC 24 |
| Finished | Oct 12 12:05:06 AM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256367059 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2256367059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3270923955 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 477653730 ps |
| CPU time | 6.37 seconds |
| Started | Oct 12 12:05:02 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270923955 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3270923955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3708925607 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 127698482 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 12:05:02 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708925607 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3708925607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3715326136 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 117819508 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:05:03 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3715326136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.3715326136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.4272194959 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 77399587 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 12:05:02 AM UTC 24 |
| Finished | Oct 12 12:05:04 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272194959 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4272194959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.461225778 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 108439038 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 12:05:03 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461225778 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.461225778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.30186260 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 297274825 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 12:05:01 AM UTC 24 |
| Finished | Oct 12 12:05:05 AM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30186260 -assert nopostproc +UVM_TESTNAME=rstmgr_bas e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.30186260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1128562651 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 209580952 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128562651 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1128562651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1828329804 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 279487140 ps |
| CPU time | 3.31 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:09 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828329804 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1828329804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.941484311 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 128082457 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:06 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941484311 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.941484311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2055828472 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 125319482 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:05:05 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2055828472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.2055828472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1733922165 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 60857062 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:06 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733922165 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1733922165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4145175029 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 124067285 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145175029 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.4145175029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.962522302 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 248189627 ps |
| CPU time | 2.46 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962522302 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.962522302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4015180148 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 487819514 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 12:05:04 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015180148 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.4015180148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1436306406 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 172774200 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:09 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1436306406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.1436306406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.365184605 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 67162006 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:05:05 AM UTC 24 |
| Finished | Oct 12 12:05:07 AM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365184605 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.365184605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1644146797 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 104652982 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644146797 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.1644146797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1125205355 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 271997407 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 12:05:05 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125205355 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1125205355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1012511228 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 425027454 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 12:05:05 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012511228 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.1012511228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2650377780 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 223449659 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:09 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2650377780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.2650377780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.3212431402 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 72106843 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212431402 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3212431402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3977558395 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 238116560 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 217740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977558395 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.3977558395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3019216559 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 436198416 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 221832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019216559 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3019216559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.884567967 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 425442105 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:09 AM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884567967 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.884567967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1176001468 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 145153476 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 12:05:07 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 217312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1176001468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.1176001468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.4171794184 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 60953720 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:08 AM UTC 24 |
| Peak memory | 207784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171794184 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4171794184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3903342093 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 124116171 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:09 AM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903342093 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.3903342093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3030294501 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 116360863 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030294501 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3030294501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1086237053 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 874614510 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 12:05:06 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086237053 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1086237053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1518819058 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 117654110 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:05:08 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1518819058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.1518819058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3386712221 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 77028478 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:05:08 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 207672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386712221 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3386712221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3953490504 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 156832125 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:05:08 AM UTC 24 |
| Finished | Oct 12 12:05:10 AM UTC 24 |
| Peak memory | 207848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953490504 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3953490504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1860750681 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 221659540 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 12:05:07 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860750681 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1860750681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1142079025 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 763736662 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 12:05:08 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142079025 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.1142079025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2433586189 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 215031078 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2433586189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.2433586189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.4239962129 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 61077316 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239962129 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4239962129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2553569814 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 154452932 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:11 AM UTC 24 |
| Peak memory | 207808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553569814 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2553569814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.4052356537 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 119246306 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 219516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052356537 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4052356537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1347676580 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 482455403 ps |
| CPU time | 2.12 seconds |
| Started | Oct 12 12:05:09 AM UTC 24 |
| Finished | Oct 12 12:05:12 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347676580 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.1347676580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.436838198 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 65314871 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 12:50:30 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436838198 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.436838198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.30322445 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 302034546 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:32 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30322445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.30322445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.2506166103 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 95033910 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:29 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506166103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2506166103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1938062906 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1040075289 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:34 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938062906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1938062906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.4022829915 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 16588339663 ps |
| CPU time | 25.31 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 244012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022829915 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4022829915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.2321182777 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 189454427 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 12:50:27 AM UTC 24 |
| Finished | Oct 12 12:50:30 AM UTC 24 |
| Peak memory | 209760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321182777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2321182777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3039721001 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 125916095 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:32 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039721001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3039721001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.2962010363 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 114119214 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:50:29 AM UTC 24 |
| Finished | Oct 12 12:50:31 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962010363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2962010363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.104451578 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2456250958 ps |
| CPU time | 8.19 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 244296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104451578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.104451578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2768560205 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 301566469 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:34 AM UTC 24 |
| Peak memory | 238708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768560205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2768560205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3926335605 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1543253075 ps |
| CPU time | 6.9 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926335605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3926335605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.388304430 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 105283321 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388304430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.388304430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2801969467 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 132813563 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:34 AM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801969467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2801969467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1391142776 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 107861843 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:50:31 AM UTC 24 |
| Finished | Oct 12 12:50:33 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391142776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1391142776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.4175061378 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 73241944 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:52 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175061378 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4175061378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1211236047 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2451675521 ps |
| CPU time | 8.54 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:59 AM UTC 24 |
| Peak memory | 243488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211236047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1211236047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2905618554 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 301491268 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905618554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2905618554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2626653083 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 172480620 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 209672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626653083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2626653083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.1039984483 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 810331909 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039984483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1039984483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1485928003 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 97412347 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485928003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1485928003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.1255407721 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 203125430 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255407721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1255407721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.1533086854 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2841813291 ps |
| CPU time | 13.16 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:51:05 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533086854 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1533086854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2597876991 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 304917722 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597876991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2597876991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3784416712 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 83124329 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784416712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3784416712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.1416209834 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 77606976 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416209834 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1416209834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.3570985414 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1971707452 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:51:01 AM UTC 24 |
| Peak memory | 244276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570985414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3570985414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.692164437 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 303815434 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692164437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.692164437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.2641207647 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 211732210 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641207647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2641207647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.2570486400 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1136741146 ps |
| CPU time | 4.78 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570486400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2570486400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3550252734 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 155152850 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550252734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3550252734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.3341488575 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 112952098 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341488575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3341488575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.4041883914 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9146349777 ps |
| CPU time | 30.31 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:51:24 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041883914 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4041883914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1305761000 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 372233589 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 12:50:51 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305761000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1305761000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.704862328 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 103529689 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:50:50 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704862328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.704862328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.68724273 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 67829186 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68724273 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.68724273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.1155376485 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1272865169 ps |
| CPU time | 5.76 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 243424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155376485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1155376485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.969689987 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 301784838 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969689987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.969689987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.1395163421 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 221196435 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:54 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395163421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1395163421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3172647171 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2008792981 ps |
| CPU time | 7.77 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:51:01 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172647171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3172647171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1457044302 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 140823498 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457044302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1457044302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.1790575390 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 120733514 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:55 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790575390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1790575390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1732270914 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4862685379 ps |
| CPU time | 22.24 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:51:17 AM UTC 24 |
| Peak memory | 220116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732270914 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1732270914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2331160968 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 269036690 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:50:57 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331160968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2331160968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2015784039 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 147117417 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:50:52 AM UTC 24 |
| Finished | Oct 12 12:50:55 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015784039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2015784039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2007586177 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 78581377 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:58 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007586177 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2007586177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.1608254676 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1273503275 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:51:03 AM UTC 24 |
| Peak memory | 243412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608254676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1608254676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4168880886 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 301120744 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:50:57 AM UTC 24 |
| Peak memory | 238776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168880886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4168880886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.3089353768 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 150991439 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:54 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089353768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3089353768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.399546161 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 936332552 ps |
| CPU time | 4.53 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399546161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.399546161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.646284661 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 93581042 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:50:57 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646284661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.646284661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.1025583645 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 252748111 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 12:50:53 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025583645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1025583645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.2942389079 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3821188274 ps |
| CPU time | 16 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:51:12 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942389079 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2942389079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.2366959274 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 303903984 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:50:58 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366959274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2366959274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2283423714 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 76737435 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:50:55 AM UTC 24 |
| Finished | Oct 12 12:50:57 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283423714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2283423714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1637205361 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 87576064 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637205361 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1637205361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.1984510034 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1273130056 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 253536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984510034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1984510034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2839220124 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 301834019 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839220124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2839220124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.552220536 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 107898546 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:58 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552220536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.552220536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.3372778961 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1251545489 ps |
| CPU time | 5.46 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:51:03 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372778961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3372778961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.659613935 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 148108444 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:59 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659613935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.659613935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3328217696 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 111732300 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:59 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328217696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3328217696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.796303384 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5496459001 ps |
| CPU time | 19.62 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:19 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796303384 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.796303384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.2637539417 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 156149564 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:59 AM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637539417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2637539417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.958376713 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 95660263 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:50:56 AM UTC 24 |
| Finished | Oct 12 12:50:58 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958376713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.958376713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.1483661172 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 58525907 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:02 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483661172 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1483661172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.3832909638 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2468676870 ps |
| CPU time | 9.38 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 243572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832909638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3832909638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2522452043 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 302566449 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:02 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522452043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2522452043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3870915780 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 218289964 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870915780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3870915780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.618076589 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1186613963 ps |
| CPU time | 5.39 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:05 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618076589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.618076589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3224327625 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 108196140 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224327625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3224327625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.3221564025 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 192746518 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:01 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221564025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3221564025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1474360356 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2676473920 ps |
| CPU time | 12.05 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:13 AM UTC 24 |
| Peak memory | 220088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474360356 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1474360356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.1553333840 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 379501454 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:02 AM UTC 24 |
| Peak memory | 219896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553333840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1553333840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.2808069007 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 112281187 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 12:50:58 AM UTC 24 |
| Finished | Oct 12 12:51:01 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808069007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2808069007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.1183832018 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 61113498 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183832018 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1183832018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.1734725080 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1970958354 ps |
| CPU time | 8.27 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 243288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734725080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1734725080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3030283949 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 302320192 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030283949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3030283949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.1316878766 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 213984640 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:02 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316878766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1316878766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.2165387547 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 994238312 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165387547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2165387547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.510097013 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 140028613 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510097013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.510097013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3567306421 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 189814312 ps |
| CPU time | 2.09 seconds |
| Started | Oct 12 12:51:00 AM UTC 24 |
| Finished | Oct 12 12:51:03 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567306421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3567306421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.248362700 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4195186521 ps |
| CPU time | 17.65 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248362700 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.248362700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.2197785152 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 116624533 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:05 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197785152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2197785152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.522484117 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 57317145 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522484117 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.522484117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2950098454 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1281876524 ps |
| CPU time | 6.35 seconds |
| Started | Oct 12 12:51:03 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 243364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950098454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2950098454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2857953837 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 301985684 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 12:51:03 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857953837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2857953837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.3378864051 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 117572821 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378864051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3378864051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.876606586 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1693959026 ps |
| CPU time | 6.62 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876606586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.876606586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3589290286 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 156897066 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:51:03 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589290286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3589290286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3927001806 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 126446351 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:05 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927001806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3927001806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.187102717 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 10457399726 ps |
| CPU time | 33.76 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:39 AM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187102717 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.187102717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.155963913 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 129779778 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:05 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155963913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.155963913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.1948134699 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 186625121 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:51:02 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948134699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1948134699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.1252856857 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 64536598 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252856857 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1252856857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.2572726938 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2447935339 ps |
| CPU time | 9.11 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572726938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2572726938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3622253812 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 301500281 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622253812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3622253812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.1241459071 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 166278559 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241459071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1241459071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.3475803604 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1295574649 ps |
| CPU time | 5.92 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475803604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3475803604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.176876090 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 95786814 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:07 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176876090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.176876090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.1573408341 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 111284369 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573408341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1573408341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.2413474759 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2569210638 ps |
| CPU time | 13.02 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:20 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413474759 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2413474759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.4108901420 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 152985455 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108901420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4108901420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.669174746 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 129624449 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 12:51:04 AM UTC 24 |
| Finished | Oct 12 12:51:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669174746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.669174746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.1748961704 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 57872071 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 12:51:07 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748961704 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1748961704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.4024003570 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1272547252 ps |
| CPU time | 7.25 seconds |
| Started | Oct 12 12:51:07 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 243428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024003570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4024003570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2211947494 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 302231804 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 12:51:07 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211947494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2211947494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.1176120109 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 137573488 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:51:06 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176120109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1176120109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.3880786400 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1475958710 ps |
| CPU time | 5.91 seconds |
| Started | Oct 12 12:51:06 AM UTC 24 |
| Finished | Oct 12 12:51:13 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880786400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3880786400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3371033446 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 151439042 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:51:06 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371033446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3371033446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.413655413 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 198618451 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 12:51:05 AM UTC 24 |
| Finished | Oct 12 12:51:09 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413655413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.413655413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.143294037 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7215133733 ps |
| CPU time | 31.48 seconds |
| Started | Oct 12 12:51:07 AM UTC 24 |
| Finished | Oct 12 12:51:40 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143294037 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.143294037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.1017106815 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 262410957 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 12:51:06 AM UTC 24 |
| Finished | Oct 12 12:51:09 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017106815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1017106815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.3298320193 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 122243118 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 12:51:06 AM UTC 24 |
| Finished | Oct 12 12:51:08 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298320193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3298320193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.3576849662 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 64904028 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:37 AM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576849662 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3576849662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.148147718 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2442765682 ps |
| CPU time | 9.16 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 244200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148147718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.148147718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1059504605 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 301573280 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:50:36 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059504605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1059504605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.1853453946 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 207249690 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:50:33 AM UTC 24 |
| Finished | Oct 12 12:50:35 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853453946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1853453946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3352168624 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1045416906 ps |
| CPU time | 4.8 seconds |
| Started | Oct 12 12:50:33 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352168624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3352168624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.2439235612 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8389092641 ps |
| CPU time | 14.65 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 244108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439235612 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2439235612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4210680904 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 111784646 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:50:36 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210680904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4210680904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2912299479 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 206197028 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 12:50:32 AM UTC 24 |
| Finished | Oct 12 12:50:35 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912299479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2912299479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.435529881 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 9378933695 ps |
| CPU time | 36.31 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435529881 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.435529881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2365102867 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 179695474 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 12:50:34 AM UTC 24 |
| Finished | Oct 12 12:50:36 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365102867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2365102867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.598431348 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 63532859 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:12 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598431348 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.598431348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.2963265211 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2433182763 ps |
| CPU time | 8.2 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963265211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2963265211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2091541222 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 302824955 ps |
| CPU time | 1.63 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:12 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091541222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2091541222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.3819025732 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 153151350 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:51:08 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819025732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3819025732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.719833041 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1622037084 ps |
| CPU time | 6.37 seconds |
| Started | Oct 12 12:51:08 AM UTC 24 |
| Finished | Oct 12 12:51:15 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719833041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.719833041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2324458694 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 166827687 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324458694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2324458694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.4061963781 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 115359008 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 12:51:07 AM UTC 24 |
| Finished | Oct 12 12:51:10 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061963781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4061963781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.2267406989 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8536591700 ps |
| CPU time | 27.98 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:39 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267406989 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2267406989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.24159237 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 416414198 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:13 AM UTC 24 |
| Peak memory | 219836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24159237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.24159237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.2467493233 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 193112831 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 12:51:09 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467493233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2467493233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3140921308 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 87482830 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:51:13 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140921308 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3140921308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.3649468495 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1270050684 ps |
| CPU time | 5.65 seconds |
| Started | Oct 12 12:51:12 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 242756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649468495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3649468495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.101313842 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 301565811 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:51:13 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 238788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101313842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.101313842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.4185571403 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 170496844 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:51:11 AM UTC 24 |
| Finished | Oct 12 12:51:14 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185571403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4185571403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.3987201159 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1857248511 ps |
| CPU time | 6.44 seconds |
| Started | Oct 12 12:51:11 AM UTC 24 |
| Finished | Oct 12 12:51:19 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987201159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3987201159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2214936838 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 101774046 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:51:12 AM UTC 24 |
| Finished | Oct 12 12:51:14 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214936838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2214936838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2201249196 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 199568277 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 12:51:11 AM UTC 24 |
| Finished | Oct 12 12:51:14 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201249196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2201249196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.969871145 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2151874226 ps |
| CPU time | 9.47 seconds |
| Started | Oct 12 12:51:13 AM UTC 24 |
| Finished | Oct 12 12:51:24 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969871145 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.969871145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.3524994417 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 267694013 ps |
| CPU time | 2 seconds |
| Started | Oct 12 12:51:11 AM UTC 24 |
| Finished | Oct 12 12:51:15 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524994417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3524994417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3501946183 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 198906553 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:51:11 AM UTC 24 |
| Finished | Oct 12 12:51:14 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501946183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3501946183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1076779445 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 63814939 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076779445 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1076779445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3244111099 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1270128184 ps |
| CPU time | 6.49 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 244088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244111099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3244111099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3434433023 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 302204406 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434433023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3434433023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2010758901 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 100331410 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010758901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2010758901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.1686520862 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1177963583 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:19 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686520862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1686520862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.545106152 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 107749951 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545106152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.545106152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2615263159 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 205065996 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615263159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2615263159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.872382650 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2967552093 ps |
| CPU time | 12.95 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:28 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872382650 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.872382650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.1675491010 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 264024111 ps |
| CPU time | 2.85 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675491010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1675491010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2029112724 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 129446481 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029112724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2029112724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.801640562 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 74999684 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:20 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801640562 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.801640562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.367472485 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2443590089 ps |
| CPU time | 8.91 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 244212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367472485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.367472485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4087426071 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 301860369 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087426071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4087426071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.33250623 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 157832538 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:16 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33250623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.33250623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.4107743758 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1776717904 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:23 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107743758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4107743758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.779390980 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 112196592 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779390980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.779390980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.1390136684 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 194827357 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 12:51:14 AM UTC 24 |
| Finished | Oct 12 12:51:17 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390136684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1390136684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3355972830 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 8629729006 ps |
| CPU time | 27.4 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:47 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355972830 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3355972830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.3860773054 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 331989810 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:19 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860773054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3860773054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.537048721 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 207078993 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:51:16 AM UTC 24 |
| Finished | Oct 12 12:51:18 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537048721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.537048721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.2904628209 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 74362472 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904628209 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2904628209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1272022986 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1275338644 ps |
| CPU time | 5.61 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272022986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1272022986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4277907285 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 303156133 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277907285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4277907285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.4152374321 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 117615458 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:20 AM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152374321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.4152374321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.197374175 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 911627113 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:24 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197374175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.197374175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3743489108 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 161861000 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743489108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3743489108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3691165949 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 207654975 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691165949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3691165949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.346281332 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 249371094 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346281332 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.346281332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.1071671167 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 144618177 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071671167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1071671167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.3582259247 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 179281067 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 12:51:18 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582259247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3582259247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3555369071 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 71873382 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555369071 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3555369071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.3071935566 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1962471016 ps |
| CPU time | 6.94 seconds |
| Started | Oct 12 12:51:22 AM UTC 24 |
| Finished | Oct 12 12:51:31 AM UTC 24 |
| Peak memory | 243372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071935566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3071935566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1577550551 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 301359697 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577550551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1577550551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.1920481196 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 139706683 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920481196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1920481196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.3150706509 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 784952871 ps |
| CPU time | 3.68 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:23 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150706509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3150706509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3729162117 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 181415742 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:51:22 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729162117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3729162117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1022901572 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 199367330 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022901572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1022901572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.1846986781 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 7139136798 ps |
| CPU time | 23.58 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:47 AM UTC 24 |
| Peak memory | 220236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846986781 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1846986781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3649564507 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 436745680 ps |
| CPU time | 2.71 seconds |
| Started | Oct 12 12:51:22 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649564507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3649564507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3283266992 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 74118064 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 12:51:19 AM UTC 24 |
| Finished | Oct 12 12:51:21 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283266992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3283266992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.3106780935 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 65864295 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106780935 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3106780935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2400413067 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2447963871 ps |
| CPU time | 8.19 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 243616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400413067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2400413067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1185605923 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 301332273 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185605923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1185605923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.2753379398 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 185774088 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753379398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2753379398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.3173758847 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1062334444 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:29 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173758847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3173758847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3660984075 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 144032566 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660984075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3660984075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.229993711 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 125739564 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229993711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.229993711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.1560744224 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3693016587 ps |
| CPU time | 16.08 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:40 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560744224 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1560744224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.22433151 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 389450115 ps |
| CPU time | 2.41 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22433151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.22433151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.1857070361 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 159578292 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857070361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1857070361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.1442710122 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 83192875 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442710122 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1442710122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.2736942090 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1955843162 ps |
| CPU time | 7.27 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:33 AM UTC 24 |
| Peak memory | 243296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736942090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2736942090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1484635456 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 302357974 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:27 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484635456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1484635456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.2432722161 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 110656676 ps |
| CPU time | 0.88 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432722161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2432722161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.4294890194 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1496745391 ps |
| CPU time | 5.78 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294890194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4294890194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4104035286 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 153322086 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104035286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4104035286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2151702432 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 250615392 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151702432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2151702432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.969723930 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 9366532122 ps |
| CPU time | 38.81 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:52:05 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969723930 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.969723930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.3817591192 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 286817795 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817591192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3817591192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.3187346511 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 66568916 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:25 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187346511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3187346511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1019898625 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 69819380 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:29 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019898625 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1019898625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.1083507699 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1271160693 ps |
| CPU time | 5.97 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 244156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083507699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1083507699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2810933694 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 301323878 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:29 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810933694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2810933694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.2113939058 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 157656979 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:27 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113939058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2113939058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.218466999 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2066223020 ps |
| CPU time | 6.89 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:33 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218466999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.218466999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4015414014 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 156408197 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:27 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015414014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4015414014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.2659502170 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 124659064 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 12:51:23 AM UTC 24 |
| Finished | Oct 12 12:51:26 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659502170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2659502170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2836861575 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1781211890 ps |
| CPU time | 6.47 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836861575 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2836861575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.3720010763 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 116196071 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:28 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720010763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3720010763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.2212391666 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 58039107 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:51:25 AM UTC 24 |
| Finished | Oct 12 12:51:27 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212391666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2212391666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1475289181 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 63079066 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475289181 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1475289181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.801478062 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1273499041 ps |
| CPU time | 5.81 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 243492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801478062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.801478062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1772614038 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 301371383 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772614038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1772614038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.1386888611 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 242815491 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:29 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386888611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1386888611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.3527303514 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1615246489 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527303514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3527303514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2746429981 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 166361355 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746429981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2746429981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.4270934439 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 130480267 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:29 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270934439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4270934439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.264608448 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 7096172212 ps |
| CPU time | 22.91 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:52 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264608448 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.264608448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.782742983 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 139065049 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782742983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.782742983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3442734639 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 186704246 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 12:51:27 AM UTC 24 |
| Finished | Oct 12 12:51:30 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442734639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3442734639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.373980020 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 84022210 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373980020 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.373980020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.991985755 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1951131079 ps |
| CPU time | 7.57 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 243416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991985755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.991985755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2264271171 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 301994399 ps |
| CPU time | 1.29 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264271171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2264271171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.185311322 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 169774133 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:37 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185311322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.185311322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.4181577872 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 876081600 ps |
| CPU time | 5.49 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181577872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4181577872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.2560624780 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 16588488011 ps |
| CPU time | 26.12 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:51:04 AM UTC 24 |
| Peak memory | 244068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560624780 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2560624780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1220244560 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 156662970 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220244560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1220244560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2104894422 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 193862086 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104894422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2104894422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.1513821341 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4262640964 ps |
| CPU time | 21.91 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:51:00 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513821341 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1513821341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.484156711 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 119452297 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 12:50:35 AM UTC 24 |
| Finished | Oct 12 12:50:38 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484156711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.484156711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1771621282 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 78869957 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771621282 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1771621282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.589765569 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2454594245 ps |
| CPU time | 9.05 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:40 AM UTC 24 |
| Peak memory | 244280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589765569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.589765569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1005876995 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 302106797 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005876995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1005876995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.678975350 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 99949055 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:51:28 AM UTC 24 |
| Finished | Oct 12 12:51:31 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678975350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.678975350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.1989442838 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1467715461 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 12:51:28 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989442838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1989442838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2969224913 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 100109008 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969224913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2969224913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.2783684512 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 229023867 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:51:28 AM UTC 24 |
| Finished | Oct 12 12:51:31 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783684512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2783684512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.237300589 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4419431618 ps |
| CPU time | 19.24 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:50 AM UTC 24 |
| Peak memory | 220148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237300589 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.237300589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.2579062416 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 117822656 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:51:29 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579062416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2579062416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3527294516 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 289917707 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 12:51:28 AM UTC 24 |
| Finished | Oct 12 12:51:31 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527294516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3527294516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.483922503 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 55246264 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483922503 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.483922503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.495768143 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1273543952 ps |
| CPU time | 6.08 seconds |
| Started | Oct 12 12:51:31 AM UTC 24 |
| Finished | Oct 12 12:51:39 AM UTC 24 |
| Peak memory | 243420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495768143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.495768143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2163442418 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 302203159 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 12:51:31 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163442418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2163442418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.2296660163 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 128611059 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:51:30 AM UTC 24 |
| Finished | Oct 12 12:51:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296660163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2296660163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.2456752441 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1938252198 ps |
| CPU time | 7.36 seconds |
| Started | Oct 12 12:51:30 AM UTC 24 |
| Finished | Oct 12 12:51:38 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456752441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2456752441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.608881736 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 105249138 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:51:31 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608881736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.608881736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.1404992542 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 270913520 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 12:51:30 AM UTC 24 |
| Finished | Oct 12 12:51:33 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404992542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1404992542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.1970747109 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 14128429753 ps |
| CPU time | 41.61 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:52:15 AM UTC 24 |
| Peak memory | 222140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970747109 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1970747109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.2018905869 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 148706784 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 12:51:31 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018905869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2018905869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.351171869 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 174412295 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 12:51:31 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351171869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.351171869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.2016281222 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 64453035 ps |
| CPU time | 0.77 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016281222 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2016281222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.3047420625 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2452166605 ps |
| CPU time | 7.92 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:43 AM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047420625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3047420625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2629016163 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 303731900 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629016163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2629016163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.2402871442 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 130858960 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:34 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402871442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2402871442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1740449489 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1279298127 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:38 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740449489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1740449489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1546078922 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 144288130 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546078922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1546078922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.1362498238 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 113230039 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362498238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1362498238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2402378830 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3248150079 ps |
| CPU time | 13.79 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:49 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402378830 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2402378830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.1261612412 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 150995946 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261612412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1261612412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.1557651801 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 197283829 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 12:51:32 AM UTC 24 |
| Finished | Oct 12 12:51:35 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557651801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1557651801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.660003282 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 75150444 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:45 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660003282 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.660003282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.3197306995 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2454627714 ps |
| CPU time | 7.79 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:43 AM UTC 24 |
| Peak memory | 244220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197306995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3197306995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2424897831 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 301900299 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424897831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2424897831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2168427564 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 81609594 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168427564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2168427564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.3478442032 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1985389371 ps |
| CPU time | 7.56 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:43 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478442032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3478442032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2359490431 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 114446234 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359490431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2359490431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.1362998974 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 253736543 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:38 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362998974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1362998974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.469711245 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 797750887 ps |
| CPU time | 3.8 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:44 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469711245 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.469711245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.4037664241 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 356532408 ps |
| CPU time | 2.29 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:37 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037664241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4037664241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.2838409593 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 124523944 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:51:34 AM UTC 24 |
| Finished | Oct 12 12:51:36 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838409593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2838409593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1156971364 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 111947272 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:45 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156971364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1156971364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.4116854235 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1326658032 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:50 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116854235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.4116854235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.2291830509 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 112855297 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291830509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2291830509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.57152714 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 303748553 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 12:51:36 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57152714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.57152714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2763591150 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 301274191 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 12:51:38 AM UTC 24 |
| Finished | Oct 12 12:51:52 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763591150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2763591150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.1372862953 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 126110630 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:51:37 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372862953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1372862953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2118153225 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1261001560 ps |
| CPU time | 5.12 seconds |
| Started | Oct 12 12:51:37 AM UTC 24 |
| Finished | Oct 12 12:51:50 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118153225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2118153225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.760728192 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 141492983 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:51:38 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760728192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.760728192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3138873504 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 107822974 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:51:37 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 209840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138873504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3138873504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.4010607491 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 125993690 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:51:38 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010607491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4010607491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2340159638 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 133484447 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 12:51:38 AM UTC 24 |
| Finished | Oct 12 12:51:42 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340159638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2340159638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.1003162448 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 70826660 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003162448 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1003162448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.1752447910 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1280324968 ps |
| CPU time | 5.65 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 243416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752447910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1752447910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3309298977 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 302578238 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309298977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3309298977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.1717869275 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 161914479 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 12:51:40 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717869275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1717869275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.4009109257 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 955794704 ps |
| CPU time | 4.42 seconds |
| Started | Oct 12 12:51:40 AM UTC 24 |
| Finished | Oct 12 12:52:09 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009109257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4009109257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.2583797238 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 251448962 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:51:40 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583797238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2583797238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.2166310528 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 14557889067 ps |
| CPU time | 43.73 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:52:29 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166310528 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2166310528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.738467644 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 366666337 ps |
| CPU time | 2.22 seconds |
| Started | Oct 12 12:51:40 AM UTC 24 |
| Finished | Oct 12 12:51:43 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738467644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.738467644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3470913885 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 135494543 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:51:40 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470913885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3470913885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.4160593453 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 62360632 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:51:57 AM UTC 24 |
| Peak memory | 209912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160593453 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4160593453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3362158073 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1270287489 ps |
| CPU time | 5.11 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 243356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362158073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3362158073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3848784090 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 301786837 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:51:58 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848784090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3848784090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.4003858810 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 225900055 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003858810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4003858810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.720495364 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 777206651 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:48 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720495364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.720495364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.443978550 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 143444816 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443978550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.443978550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2520428022 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 253904405 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520428022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2520428022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.62694748 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3322341960 ps |
| CPU time | 12.14 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:52:09 AM UTC 24 |
| Peak memory | 220212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62694748 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.62694748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.3399728750 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 341900459 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:47 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399728750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3399728750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.3022157338 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 179247860 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:51:43 AM UTC 24 |
| Finished | Oct 12 12:51:46 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022157338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3022157338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.3351835177 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 77278192 ps |
| CPU time | 0.83 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351835177 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3351835177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.2388985794 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1267460681 ps |
| CPU time | 4.92 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:55 AM UTC 24 |
| Peak memory | 244080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388985794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2388985794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3502667232 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 301190901 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502667232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3502667232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.40488834 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 243273147 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:52:01 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40488834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.40488834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.4166250936 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1548463349 ps |
| CPU time | 5.83 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166250936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4166250936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3286601181 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 106073651 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286601181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3286601181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.2413733621 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 126733824 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:51:45 AM UTC 24 |
| Finished | Oct 12 12:51:58 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413733621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2413733621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.896875264 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 12161910812 ps |
| CPU time | 38.95 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:52:29 AM UTC 24 |
| Peak memory | 220088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896875264 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.896875264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.2985578662 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 131281964 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:58 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985578662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2985578662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.2454228209 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 83855371 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:57 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454228209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2454228209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.4026398193 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 77995739 ps |
| CPU time | 0.75 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:01 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026398193 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4026398193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.310861082 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2439044655 ps |
| CPU time | 7.54 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:08 AM UTC 24 |
| Peak memory | 243392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310861082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.310861082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.939612369 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 301526711 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 238160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939612369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.939612369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.2102446176 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 162499584 ps |
| CPU time | 0.82 seconds |
| Started | Oct 12 12:51:50 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102446176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2102446176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.4271166155 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1032839338 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 12:51:50 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271166155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4271166155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.372754176 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 109736369 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 12:51:50 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372754176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.372754176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.652438843 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 188322856 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:51:48 AM UTC 24 |
| Finished | Oct 12 12:51:51 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652438843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.652438843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.1650804204 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2002871664 ps |
| CPU time | 6.51 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:07 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650804204 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1650804204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.1187315293 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 129281017 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 12:51:50 AM UTC 24 |
| Finished | Oct 12 12:52:13 AM UTC 24 |
| Peak memory | 218964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187315293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1187315293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.2426756350 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 103533345 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 12:51:50 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426756350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2426756350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.3879011859 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 63820347 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:50:39 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879011859 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3879011859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1085745747 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 302570361 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 239700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085745747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1085745747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.2707227901 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 189455484 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707227901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2707227901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.618501036 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1419082687 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618501036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.618501036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1958600179 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 16567583903 ps |
| CPU time | 30.82 seconds |
| Started | Oct 12 12:50:39 AM UTC 24 |
| Finished | Oct 12 12:51:12 AM UTC 24 |
| Peak memory | 244076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958600179 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1958600179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2958894599 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 95166395 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:50:40 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958894599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2958894599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2771704140 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 115665220 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:50:37 AM UTC 24 |
| Finished | Oct 12 12:50:39 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771704140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2771704140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1500875627 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8253810821 ps |
| CPU time | 37.59 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:51:17 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500875627 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1500875627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.598564458 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 148077644 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:50:41 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598564458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.598564458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.2890206664 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 111904033 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:50:38 AM UTC 24 |
| Finished | Oct 12 12:50:40 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890206664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2890206664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3217859291 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 61784029 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217859291 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3217859291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.3154054552 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1262509169 ps |
| CPU time | 5.09 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:20 AM UTC 24 |
| Peak memory | 243608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154054552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3154054552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.83206073 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 301819616 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 238780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83206073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.83206073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.310370118 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 185953350 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:01 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310370118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.310370118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2977501198 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1089492069 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977501198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2977501198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.492525959 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 92108467 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492525959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.492525959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.2426662489 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 192485900 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426662489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2426662489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.1021079841 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6366993140 ps |
| CPU time | 22.41 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021079841 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1021079841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.3634968474 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 138623212 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:03 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634968474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3634968474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.1143532946 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 123410438 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:51:58 AM UTC 24 |
| Finished | Oct 12 12:52:02 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143532946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1143532946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.127956359 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 60315125 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127956359 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.127956359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2096904900 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1271619874 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:21 AM UTC 24 |
| Peak memory | 243472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096904900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2096904900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3359637043 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 302001205 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:17 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359637043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3359637043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.1900786392 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 109037153 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900786392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1900786392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2518158084 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2150082507 ps |
| CPU time | 7.45 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:23 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518158084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2518158084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2055307257 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 97201975 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055307257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2055307257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.3601808654 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 119233470 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:06 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601808654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3601808654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.1743586868 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3498900439 ps |
| CPU time | 13.23 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:29 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743586868 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1743586868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.3450533840 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 138401162 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 12:52:03 AM UTC 24 |
| Finished | Oct 12 12:52:17 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450533840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3450533840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.432998028 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 126399696 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:52:01 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432998028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.432998028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.2051869645 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 75036187 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051869645 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2051869645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.2297210977 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1267753143 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:16 AM UTC 24 |
| Peak memory | 243360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297210977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2297210977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1982973201 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 302485463 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982973201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1982973201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1052686155 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 128243144 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 12:52:05 AM UTC 24 |
| Finished | Oct 12 12:52:34 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052686155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1052686155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.3883505804 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1785428221 ps |
| CPU time | 5.96 seconds |
| Started | Oct 12 12:52:05 AM UTC 24 |
| Finished | Oct 12 12:52:39 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883505804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3883505804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1589062541 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 106456258 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589062541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1589062541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2428782518 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4148437364 ps |
| CPU time | 13.46 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:24 AM UTC 24 |
| Peak memory | 220176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428782518 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2428782518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2030420366 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 138287246 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030420366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2030420366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.2239586735 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 136990588 ps |
| CPU time | 1 seconds |
| Started | Oct 12 12:52:05 AM UTC 24 |
| Finished | Oct 12 12:52:27 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239586735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2239586735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.2823590034 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 73526303 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:22 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823590034 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2823590034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2390271036 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1970880733 ps |
| CPU time | 6.55 seconds |
| Started | Oct 12 12:52:12 AM UTC 24 |
| Finished | Oct 12 12:52:27 AM UTC 24 |
| Peak memory | 243648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390271036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2390271036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2542052726 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 304242333 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:22 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542052726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2542052726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.440891009 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 142738483 ps |
| CPU time | 0.75 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440891009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.440891009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.2854881763 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1573507295 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 12:52:12 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854881763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2854881763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.900435428 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 143774959 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:52:12 AM UTC 24 |
| Finished | Oct 12 12:52:21 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900435428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.900435428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.2191017912 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 242458535 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:52:10 AM UTC 24 |
| Finished | Oct 12 12:52:12 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191017912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2191017912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.2041134449 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6266578957 ps |
| CPU time | 19.11 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:40 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041134449 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2041134449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.932501046 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 394369239 ps |
| CPU time | 2.11 seconds |
| Started | Oct 12 12:52:12 AM UTC 24 |
| Finished | Oct 12 12:52:22 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932501046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.932501046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.3947111046 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 110289706 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:52:12 AM UTC 24 |
| Finished | Oct 12 12:52:21 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947111046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3947111046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.393975847 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 61481158 ps |
| CPU time | 0.66 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393975847 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.393975847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.68242268 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1971008292 ps |
| CPU time | 6.61 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 243864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68242268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.68242268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1391666035 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 302374332 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391666035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1391666035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.4205054818 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 171947612 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205054818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4205054818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.799356363 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1607493771 ps |
| CPU time | 6.13 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799356363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.799356363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.839177454 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 164155282 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839177454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.839177454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.259565379 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 202901378 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:22 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259565379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.259565379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.2901674196 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2908850725 ps |
| CPU time | 12.22 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901674196 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2901674196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.3751381741 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 109784933 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:33 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751381741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3751381741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.3072025724 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 108817435 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072025724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3072025724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1830531000 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 82869429 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830531000 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1830531000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2469631256 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1268991334 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:30 AM UTC 24 |
| Peak memory | 243348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469631256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2469631256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3497079906 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 302037153 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497079906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3497079906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3987556580 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 114857511 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:25 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987556580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3987556580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3122576153 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1703711641 ps |
| CPU time | 5.82 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:30 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122576153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3122576153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1399905654 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 145074242 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 209776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399905654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1399905654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.4060360538 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 256983938 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 209708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060360538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4060360538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2604999693 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 158532260 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604999693 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2604999693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.369950461 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 123996160 ps |
| CPU time | 1.49 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369950461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.369950461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.3785995080 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 73659747 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 12:52:20 AM UTC 24 |
| Finished | Oct 12 12:52:25 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785995080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3785995080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.1157496969 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 69487395 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:27 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157496969 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1157496969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.3362882523 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1269047500 ps |
| CPU time | 5.12 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:31 AM UTC 24 |
| Peak memory | 244092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362882523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3362882523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1587956880 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 302409304 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:27 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587956880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1587956880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.3619994438 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 104524730 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:32 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619994438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3619994438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2399339305 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 882792385 ps |
| CPU time | 3.77 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:35 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399339305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2399339305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3599487429 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 94199910 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:27 AM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599487429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3599487429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.559435366 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 223663401 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:33 AM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559435366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.559435366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.142871586 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5195650619 ps |
| CPU time | 17.08 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:43 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142871586 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.142871586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.1377117863 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 111942622 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:33 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377117863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1377117863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.2373789246 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 227787730 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:52:21 AM UTC 24 |
| Finished | Oct 12 12:52:33 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373789246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2373789246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.587277119 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 73120470 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587277119 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.587277119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3457237796 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1271004864 ps |
| CPU time | 4.99 seconds |
| Started | Oct 12 12:52:26 AM UTC 24 |
| Finished | Oct 12 12:52:39 AM UTC 24 |
| Peak memory | 243132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457237796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3457237796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1627633205 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 301866645 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627633205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1627633205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.4211221747 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 80415851 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211221747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4211221747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.286674106 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1346711096 ps |
| CPU time | 4.57 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:30 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286674106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.286674106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.458544431 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 100610584 ps |
| CPU time | 0.91 seconds |
| Started | Oct 12 12:52:26 AM UTC 24 |
| Finished | Oct 12 12:52:35 AM UTC 24 |
| Peak memory | 208932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458544431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.458544431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.1961522660 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 194442023 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961522660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1961522660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.1885518925 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3534940958 ps |
| CPU time | 15.59 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:52 AM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885518925 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1885518925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.1581528205 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 115654561 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:52:26 AM UTC 24 |
| Finished | Oct 12 12:52:35 AM UTC 24 |
| Peak memory | 209592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581528205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1581528205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.3249917219 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 99531046 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 12:52:24 AM UTC 24 |
| Finished | Oct 12 12:52:26 AM UTC 24 |
| Peak memory | 209728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249917219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3249917219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2970132737 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 77451994 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970132737 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2970132737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.1108404350 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1265999438 ps |
| CPU time | 5.15 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:42 AM UTC 24 |
| Peak memory | 244220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108404350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1108404350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2015996821 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 301317698 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015996821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2015996821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.2725271602 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 140189754 ps |
| CPU time | 0.95 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:37 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725271602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2725271602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.4203339344 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1143408448 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:42 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203339344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4203339344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.149522596 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 110989852 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149522596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.149522596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2082474355 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 192903881 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082474355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2082474355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2816970560 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 6013366070 ps |
| CPU time | 20.54 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:57 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816970560 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2816970560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.2758255954 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 150191137 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758255954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2758255954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.2267969801 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 148571051 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:52:35 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267969801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2267969801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2106020616 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 66536589 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:48 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106020616 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2106020616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3420459199 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1274253000 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:53 AM UTC 24 |
| Peak memory | 243044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420459199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3420459199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1151629414 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 313318464 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:48 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151629414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1151629414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.271907732 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 168900648 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271907732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.271907732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.3730300335 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1300200851 ps |
| CPU time | 5.26 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:52 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730300335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3730300335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2656096798 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 153279576 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:48 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656096798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2656096798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.3426629081 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 205616075 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 12:52:36 AM UTC 24 |
| Finished | Oct 12 12:52:38 AM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426629081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3426629081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1068529812 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1412581316 ps |
| CPU time | 5.04 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:52 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068529812 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1068529812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.1135460497 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 152451491 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:49 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135460497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1135460497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.3132914271 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 90781901 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 12:52:46 AM UTC 24 |
| Finished | Oct 12 12:52:48 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132914271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3132914271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4111889467 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 73900260 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:43 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111889467 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4111889467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3707824337 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1283045903 ps |
| CPU time | 7.56 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 243780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707824337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3707824337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.439098528 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 301986374 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 239636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439098528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.439098528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.3521470528 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 197443603 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521470528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3521470528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1409223092 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 984294712 ps |
| CPU time | 4.42 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409223092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1409223092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3008277363 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 142446740 ps |
| CPU time | 1.62 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008277363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3008277363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.879951978 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 237205292 ps |
| CPU time | 1.6 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879951978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.879951978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.2633114738 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2420016252 ps |
| CPU time | 13.89 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:55 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633114738 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2633114738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.2323150727 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 124731282 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323150727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2323150727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1105846982 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 142862005 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:50:40 AM UTC 24 |
| Finished | Oct 12 12:50:42 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105846982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1105846982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.3621342785 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 65248782 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621342785 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3621342785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2863776248 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1273712018 ps |
| CPU time | 6.07 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 243836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863776248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2863776248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1975674803 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 301824941 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975674803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1975674803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.3060369641 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 204986800 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:43 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060369641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3060369641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.4261061342 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 923337585 ps |
| CPU time | 4.48 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261061342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4261061342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2119680189 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 160157221 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119680189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2119680189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2663188436 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 194745650 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:44 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663188436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2663188436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1355057925 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 16524999633 ps |
| CPU time | 55.31 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:51:40 AM UTC 24 |
| Peak memory | 220152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355057925 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1355057925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.1754690868 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 315203532 ps |
| CPU time | 2.53 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754690868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1754690868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.247434832 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 145285886 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:50:41 AM UTC 24 |
| Finished | Oct 12 12:50:43 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247434832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.247434832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.4086363573 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 74563696 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086363573 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4086363573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2763369171 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 301533619 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763369171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2763369171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.662628981 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 149330224 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662628981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.662628981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3105861559 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 951750797 ps |
| CPU time | 4.61 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:49 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105861559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3105861559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1727065342 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 107107801 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727065342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1727065342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2908690576 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 120289582 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 12:50:43 AM UTC 24 |
| Finished | Oct 12 12:50:45 AM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908690576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2908690576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.2887850086 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 13558051428 ps |
| CPU time | 53 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:51:39 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887850086 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2887850086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.2717959680 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 131369113 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 218972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717959680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2717959680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.4058268379 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 247944094 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:50:44 AM UTC 24 |
| Finished | Oct 12 12:50:47 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058268379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4058268379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3913645013 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 78079302 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913645013 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3913645013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.56439862 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1267450126 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:53 AM UTC 24 |
| Peak memory | 243300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56439862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.56439862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3358799193 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 302581225 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:49 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358799193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3358799193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.673956034 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 180369402 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673956034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.673956034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2325260745 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1221453562 ps |
| CPU time | 5.38 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:52 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325260745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2325260745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2212856119 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 104440457 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212856119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2212856119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2838728230 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 188361710 ps |
| CPU time | 1.5 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838728230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2838728230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.2629402125 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 8248933871 ps |
| CPU time | 27.79 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:51:15 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629402125 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2629402125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.239756118 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 496626245 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239756118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.239756118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3980545653 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 116870720 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980545653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3980545653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3916515362 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 87575891 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 12:50:49 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916515362 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3916515362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.974883427 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1270966218 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 12:50:47 AM UTC 24 |
| Finished | Oct 12 12:50:55 AM UTC 24 |
| Peak memory | 244240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974883427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.974883427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3106379366 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 300706324 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:50:48 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 238784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106379366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3106379366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.2123196332 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 71654863 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123196332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2123196332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.434889761 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1652081470 ps |
| CPU time | 8.45 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:56 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434889761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.434889761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3157358067 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 147110405 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 12:50:47 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157358067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3157358067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2444153484 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 188492028 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 12:50:46 AM UTC 24 |
| Finished | Oct 12 12:50:48 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444153484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2444153484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1138801164 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 4948273359 ps |
| CPU time | 21.86 seconds |
| Started | Oct 12 12:50:48 AM UTC 24 |
| Finished | Oct 12 12:51:11 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138801164 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1138801164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4203647170 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 444329005 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 12:50:47 AM UTC 24 |
| Finished | Oct 12 12:50:51 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203647170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4203647170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1558353541 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 242777090 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 12:50:47 AM UTC 24 |
| Finished | Oct 12 12:50:50 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558353541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1558353541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
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