Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	99.03	92.19	96.84	94.74	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.26	99.92	89.38	71.29	94.74	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.66	97.10	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T14,T15

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T3,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T14	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T19,T20	Yes	T1,T19,T20	INPUT
tl_i.a_user.rsvd[9:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T20,T24,T25	Yes	T20,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T16	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T18,T4	Yes	T1,T18,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T28,T29	Yes	T2,T28,T29	INPUT
edn_i[3].edn_req	Yes	Yes	T14,T17,T30	Yes	T14,T17,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T31,T32	Yes	T3,T31,T32	INPUT
edn_i[5].edn_req	Yes	Yes	T8,T5,T33	Yes	T8,T5,T33	INPUT
edn_i[6].edn_req	Yes	Yes	T31,T34,T35	Yes	T31,T34,T35	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T18,T20	Yes	T1,T18,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T20,T8,T36	Yes	T1,T20,T8	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T18,T20	Yes	T1,T18,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T15,T27,T37	Yes	T15,T27,T37	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T38,T39,T40	Yes	T15,T37,T41	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T15,T27,T37	Yes	T15,T27,T37	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T29,T32,T42	Yes	T29,T43,T32	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T29,T32,T44	Yes	T29,T32,T42	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T29,T43	Yes	T2,T29,T43	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T14,T17,T30	Yes	T14,T17,T30	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T17,T32,T45	Yes	T14,T17,T32	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T14,T17,T30	Yes	T14,T17,T30	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T31,T32,T38	Yes	T31,T32,T38	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T32,T38,T39	Yes	T32,T38,T39	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T31,T32,T38	Yes	T31,T32,T38	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T8,T5,T33	Yes	T8,T5,T33	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T5,T33,T32	Yes	T5,T33,T32	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T8,T5,T33	Yes	T8,T5,T33	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T34,T29,T46	Yes	T34,T29,T46	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T35,T46,T47	Yes	T35,T29,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T31,T34,T35	Yes	T31,T34,T35	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T20,T36,T9	Yes	T20,T8,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T17,T20,T8	Yes	T20,T36,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T16,T14	Yes	T1,T16,T14	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T3,T19	Yes	T2,T3,T19	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T16,T14	Yes	T1,T16,T14	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T3,T19	Yes	T2,T3,T19	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T20,T36,T24	Yes	T20,T36,T24	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T20,T36	Yes	T2,T20,T36	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217892640	217745998	0	0
CsrngAppIfOut_A	217892640	217745998	0	0
FpvSecCmCntAlertCheck_A	217892640	135	0	0
FpvSecCmMainFsmCheck_A	217892640	90	0	0
FpvSecCmRegWeOnehotCheck_A	217892640	90	0	0
IntrEdnCmdReqDoneKnownO_A	217892640	217745998	0	0
TlAReadyKnownO_A	217892640	217745998	0	0
TlDValidKnownO_A	217892640	217745998	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217892640	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[0].EdnDataStable_A	217892640	6904	0	164
gen_edn_if_asserts[0].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[1].EdnDataStable_A	217892640	375	0	21
gen_edn_if_asserts[1].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[2].EdnDataStable_A	217892640	384	0	19
gen_edn_if_asserts[2].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[3].EdnDataStable_A	217892640	326	0	20
gen_edn_if_asserts[3].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[4].EdnDataStable_A	217892640	315	0	14
gen_edn_if_asserts[4].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[5].EdnDataStable_A	217892640	329	0	14
gen_edn_if_asserts[5].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217892640	135206	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217892640	571855	0	0
gen_edn_if_asserts[6].EdnDataStable_A	217892640	210	0	15
gen_edn_if_asserts[6].EdnEndPointOut_A	217892640	217745998	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217892640	135206	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135	0	0
T2	1213	1	0	0
T3	2068	0	0	0
T4	2899	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T21	0	10	0	0
T35	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	1422	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	90	0	0
T21	19231	10	0	0
T22	35289	20	0	0
T23	54157	20	0	0
T53	0	20	0	0
T54	0	20	0	0
T55	1049	0	0	0
T56	1194	0	0	0
T57	2321	0	0	0
T58	1344	0	0	0
T59	1907	0	0	0
T60	807	0	0	0
T61	119865	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	6904	0	164
T1	1555	4	0	1
T2	1213	0	0	0
T3	2068	0	0	0
T4	2899	0	0	0
T8	0	2	0	0
T9	0	37	0	1
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	3	0	1
T19	1312	0	0	0
T20	142424	61	0	0
T24	0	31	0	0
T36	0	20	0	1
T52	0	3	0	1
T62	0	9	0	1
T63	0	6	0	1
T64	0	0	0	1
T65	0	0	0	1
T66	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	375	0	21
T15	1850	4	0	1
T31	1329	0	0	0
T37	0	8	0	1
T38	0	61	0	1
T39	0	59	0	1
T40	0	3	0	1
T41	0	18	0	1
T64	801	0	0	0
T65	12402	0	0	0
T66	1367	0	0	0
T68	794	0	0	0
T70	0	3	0	0
T71	0	3	0	1
T72	0	3	0	0
T73	0	3	0	0
T74	1491	0	0	0
T75	1695	0	0	0
T76	1087	0	0	0
T77	16276	0	0	0
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	384	0	19
T27	2241	0	0	0
T29	2020	3	0	0
T32	0	8	0	1
T42	0	3	0	1
T43	2078	3	0	0
T44	0	3	0	0
T46	1142	0	0	0
T50	2076	0	0	0
T51	1004	0	0	0
T78	0	0	0	1
T79	0	0	0	1
T81	0	3	0	0
T82	0	4	0	1
T83	0	27	0	1
T84	0	3	0	0
T85	0	3	0	0
T86	1230	0	0	0
T87	843	0	0	0
T88	1081	0	0	0
T89	2549	0	0	0
T90	0	0	0	1
T91	0	0	0	1
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	326	0	20
T4	2899	0	0	0
T8	2390	0	0	0
T14	1611	4	0	1
T17	1039	3	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T30	0	3	0	1
T32	0	8	0	1
T36	16583	0	0	0
T45	0	3	0	0
T52	1422	0	0	0
T67	606	0	0	0
T93	0	0	0	1
T94	0	4	0	1
T95	0	3	0	0
T96	0	3	0	1
T97	0	3	0	0
T98	0	4	0	1
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	315	0	14
T6	1693	0	0	0
T7	1170	0	0	0
T31	1329	3	0	0
T32	0	40	0	1
T38	0	57	0	1
T39	0	64	0	1
T65	12402	0	0	0
T66	1367	0	0	0
T69	1657	0	0	0
T74	1491	0	0	0
T75	1695	0	0	0
T76	1087	0	0	0
T77	16276	0	0	0
T99	0	45	0	1
T102	0	3	0	1
T103	0	3	0	1
T104	0	3	0	1
T105	0	4	0	1
T106	0	3	0	0
T107	0	0	0	1
T108	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	329	0	14
T5	1070	0	0	0
T8	2390	3	0	0
T9	1709	0	0	0
T12	0	0	0	1
T13	1565	0	0	0
T24	184855	0	0	0
T32	0	44	0	1
T36	16583	0	0	0
T38	0	53	0	1
T39	0	16	0	1
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T87	843	3	0	1
T109	0	4	0	1
T110	0	3	0	0
T111	0	3	0	1
T112	0	3	0	0
T113	0	3	0	0
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	571855	0	0
T1	1555	148	0	0
T2	1213	579	0	0
T3	2068	527	0	0
T4	2899	1106	0	0
T14	1611	21	0	0
T16	1244	1143	0	0
T17	1039	82	0	0
T18	1420	100	0	0
T19	1312	1236	0	0
T20	142424	1422	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	210	0	15
T29	2020	3	0	0
T33	931	0	0	0
T34	1215	3	0	0
T35	784	0	0	0
T46	0	3	0	0
T47	0	72	0	1
T57	0	3	0	0
T117	0	3	0	0
T118	0	3	0	0
T119	0	4	0	1
T120	0	3	0	1
T121	0	3	0	1
T122	1053	0	0	0
T123	1195	0	0	0
T124	5712	0	0	0
T125	592	0	0	0
T126	1827	0	0	0
T127	1656	0	0	0
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1
T132	0	0	0	1
T133	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	135206	0	0
T2	1213	615	0	0
T3	2068	602	0	0
T4	2899	1141	0	0
T5	0	286	0	0
T6	0	645	0	0
T7	0	604	0	0
T13	0	290	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T67	0	26	0	0
T68	0	441	0	0
T69	0	884	0	0