Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218399214	10086193	0	0
boot_gen_cmd_rd_A	218399214	62004	0	0
boot_ins_cmd_rd_A	218399214	72036	0	0
ctrl_rd_A	218399214	62965	0	0
err_code_test_rd_A	218399214	61635	0	0
intr_enable_rd_A	218399214	70001	0	0
max_num_reqs_between_reseeds_rd_A	218399214	72673	0	0
regwen_rd_A	218399214	72429	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	10086193	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	49386	0	0
T24	184855	77642	0	0
T25	0	35574	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	427774	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T143	0	347862	0	0
T156	0	94437	0	0
T157	0	251941	0	0
T158	0	207885	0	0
T159	0	295888	0	0
T160	0	98733	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	62004	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1752	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	11878	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T157	0	3601	0	0
T158	0	5354	0	0
T161	0	46	0	0
T162	0	42	0	0
T163	0	4	0	0
T164	0	22	0	0
T165	0	5	0	0
T166	0	10	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	72036	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1743	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	13644	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T157	0	4303	0	0
T158	0	6697	0	0
T161	0	26	0	0
T162	0	17	0	0
T164	0	22	0	0
T165	0	16	0	0
T167	0	12	0	0
T168	0	38	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	62965	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1302	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	11654	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T69	0	3	0	0
T77	0	2	0	0
T148	0	2	0	0
T157	0	3807	0	0
T158	0	5502	0	0
T161	0	2	0	0
T162	0	13	0	0
T169	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	61635	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1572	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	11318	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T157	0	3655	0	0
T158	0	5640	0	0
T161	0	20	0	0
T162	0	26	0	0
T163	0	1	0	0
T164	0	12	0	0
T165	0	5	0	0
T170	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	70001	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1639	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	12402	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T77	0	34	0	0
T157	0	3947	0	0
T158	0	6202	0	0
T169	0	66	0	0
T171	0	104	0	0
T172	0	25	0	0
T173	0	16	0	0
T174	0	16	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	72673	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1573	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	13729	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T157	0	4525	0	0
T158	0	6415	0	0
T161	0	7	0	0
T162	0	18	0	0
T163	0	107	0	0
T164	0	6	0	0
T165	0	5	0	0
T170	0	25	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218399214	72429	0	0
T8	2390	0	0	0
T9	1709	0	0	0
T13	1565	0	0	0
T20	142424	1642	0	0
T24	184855	0	0	0
T36	16583	0	0	0
T52	1422	0	0	0
T61	0	13331	0	0
T62	1051	0	0	0
T63	6170	0	0	0
T67	606	0	0	0
T157	0	4604	0	0
T158	0	6551	0	0
T161	0	20	0	0
T162	0	13	0	0
T163	0	75	0	0
T164	0	5	0	0
T165	0	13	0	0
T170	0	37	0	0