KEYMGR Simulation Results

Thursday February 08 2024 20:05:57 UTC

GitHub Revision: 5470b05185

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2313004684

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 56.610s 2.006ms 50 50 100.00
V1 random keymgr_random 37.310s 1.086ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.560s 44.374us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.430s 51.521us 17 20 85.00
V1 csr_bit_bash keymgr_csr_bit_bash 24.500s 879.099us 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 14.250s 754.818us 4 5 80.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.840s 73.020us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.430s 51.521us 17 20 85.00
keymgr_csr_aliasing 14.250s 754.818us 4 5 80.00
V1 TOTAL 151 155 97.42
V2 cfgen_during_op keymgr_cfg_regwen 1.687m 2.167ms 49 50 98.00
V2 sideload keymgr_sideload 1.063m 21.120ms 50 50 100.00
keymgr_sideload_kmac 53.500s 7.579ms 50 50 100.00
keymgr_sideload_aes 54.090s 4.110ms 50 50 100.00
keymgr_sideload_otbn 1.009m 2.263ms 49 50 98.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 27.570s 6.600ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 11.560s 500.262us 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.173m 4.560ms 47 50 94.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.456m 32.891ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.243m 10.158ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 24.220s 1.132ms 50 50 100.00
V2 stress_all keymgr_stress_all 8.139m 19.965ms 49 50 98.00
V2 intr_test keymgr_intr_test 1.050s 22.165us 50 50 100.00
V2 alert_test keymgr_alert_test 1.020s 34.925us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.210s 1.824ms 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.210s 1.824ms 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.560s 44.374us 5 5 100.00
keymgr_csr_rw 1.430s 51.521us 17 20 85.00
keymgr_csr_aliasing 14.250s 754.818us 4 5 80.00
keymgr_same_csr_outstanding 3.530s 341.632us 16 20 80.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.560s 44.374us 5 5 100.00
keymgr_csr_rw 1.430s 51.521us 17 20 85.00
keymgr_csr_aliasing 14.250s 754.818us 4 5 80.00
keymgr_same_csr_outstanding 3.530s 341.632us 16 20 80.00
V2 TOTAL 730 740 98.65
V2S sec_cm_additional_check keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
keymgr_tl_intg_err 33.970s 5.737ms 16 20 80.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 36.380s 2.440ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 36.380s 2.440ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 36.380s 2.440ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 36.380s 2.440ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 15.220s 446.821us 12 20 60.00
V2S prim_count_check keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 33.970s 5.737ms 16 20 80.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 36.380s 2.440ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.687m 2.167ms 49 50 98.00
V2S sec_cm_reseed_config_regwen keymgr_random 37.310s 1.086ms 50 50 100.00
keymgr_csr_rw 1.430s 51.521us 17 20 85.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 37.310s 1.086ms 50 50 100.00
keymgr_csr_rw 1.430s 51.521us 17 20 85.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 37.310s 1.086ms 50 50 100.00
keymgr_csr_rw 1.430s 51.521us 17 20 85.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 11.560s 500.262us 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.243m 10.158ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.243m 10.158ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 37.310s 1.086ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 55.130s 5.928ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 55.010s 1.836ms 49 50 98.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 11.560s 500.262us 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 55.010s 1.836ms 49 50 98.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 55.010s 1.836ms 49 50 98.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 55.010s 1.836ms 49 50 98.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 1.813m 4.601ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 55.010s 1.836ms 49 50 98.00
V2S TOTAL 152 165 92.12
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 13.970s 187.996us 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 1079 1110 97.21

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 16 16 11 68.75
V2S 6 6 3 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.80 99.10 97.95 98.37 100.00 99.11 98.41 91.63

Failure Buckets

Past Results