Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4285109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

602769

1

T1

144

T2

456

T3

458

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4484139	1			T1	6538		T2	1731		T3	646
values[0x0]	200051	1			T1	40		T2	161		T3	104
values[0x1]	203688	1			T1	46		T2	172		T3	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2914005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1973873

1

T1

2299

T2

968

T3

551

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15767	1			T1	21		T2	8		T3	2
valid_sources[0x01]	17248	1			T1	28		T2	7		T3	3
valid_sources[0x02]	17138	1			T1	30		T2	9		T13	10
valid_sources[0x03]	16342	1			T1	25		T2	8		T3	11
valid_sources[0x04]	18042	1			T1	28		T2	4		T3	1
valid_sources[0x05]	16520	1			T1	48		T2	4		T3	2
valid_sources[0x06]	15952	1			T1	45		T2	7		T13	5
valid_sources[0x07]	16128	1			T1	22		T2	8		T13	1
valid_sources[0x08]	71404	1			T1	33		T2	3		T3	3
valid_sources[0x09]	19740	1			T1	18		T2	7		T13	5
valid_sources[0x0a]	19918	1			T1	56		T2	9		T13	11
valid_sources[0x0b]	17750	1			T1	12		T2	11		T13	13
valid_sources[0x0c]	16734	1			T1	32		T2	8		T3	7
valid_sources[0x0d]	18265	1			T1	39		T2	14		T3	2
valid_sources[0x0e]	19494	1			T1	30		T2	10		T13	10
valid_sources[0x0f]	22013	1			T1	47		T2	12		T3	1
valid_sources[0x10]	17848	1			T1	25		T2	2		T3	5
valid_sources[0x11]	15298	1			T1	17		T2	13		T3	5
valid_sources[0x12]	33792	1			T1	22		T2	11		T13	1
valid_sources[0x13]	22644	1			T1	36		T2	13		T13	6
valid_sources[0x14]	25726	1			T1	20		T2	6		T13	17
valid_sources[0x15]	19636	1			T1	27		T2	15		T13	7
valid_sources[0x16]	17116	1			T1	40		T2	12		T3	4
valid_sources[0x17]	16197	1			T1	31		T2	7		T13	2
valid_sources[0x18]	25378	1			T1	28		T2	9		T3	12
valid_sources[0x19]	15861	1			T1	36		T2	5		T3	4
valid_sources[0x1a]	17081	1			T1	28		T2	6		T3	1
valid_sources[0x1b]	18411	1			T1	23		T2	5		T3	9
valid_sources[0x1c]	16548	1			T1	11		T2	2		T3	19
valid_sources[0x1d]	16576	1			T1	23		T2	10		T3	3
valid_sources[0x1e]	16748	1			T1	46		T2	6		T13	14
valid_sources[0x1f]	16012	1			T1	28		T2	8		T13	24
valid_sources[0x20]	15774	1			T1	37		T2	4		T3	11
valid_sources[0x21]	17210	1			T1	19		T2	11		T3	2
valid_sources[0x22]	17338	1			T1	17		T2	1		T3	3
valid_sources[0x23]	17202	1			T1	16		T2	9		T3	7
valid_sources[0x24]	16273	1			T1	31		T2	7		T3	2
valid_sources[0x25]	17089	1			T1	13		T2	8		T13	6
valid_sources[0x26]	16070	1			T1	18		T2	17		T3	3
valid_sources[0x27]	16324	1			T1	16		T2	12		T3	7
valid_sources[0x28]	16286	1			T1	24		T2	9		T3	7
valid_sources[0x29]	16401	1			T1	23		T2	8		T3	1
valid_sources[0x2a]	15704	1			T1	4		T2	5		T3	3
valid_sources[0x2b]	16459	1			T1	19		T2	5		T3	5
valid_sources[0x2c]	16496	1			T1	39		T2	13		T3	4
valid_sources[0x2d]	15336	1			T1	38		T2	8		T3	3
valid_sources[0x2e]	18903	1			T1	36		T2	10		T3	3
valid_sources[0x2f]	19511	1			T1	20		T2	12		T3	4
valid_sources[0x30]	32920	1			T1	20		T2	5		T3	1
valid_sources[0x31]	26723	1			T1	27		T2	2		T13	4
valid_sources[0x32]	15714	1			T1	21		T2	7		T3	6
valid_sources[0x33]	16663	1			T1	11		T2	6		T3	2
valid_sources[0x34]	22616	1			T1	3		T2	6		T3	1
valid_sources[0x35]	17701	1			T1	49		T2	9		T3	2
valid_sources[0x36]	15989	1			T1	15		T2	13		T3	3
valid_sources[0x37]	24502	1			T1	18		T2	14		T3	5
valid_sources[0x38]	26675	1			T1	8		T2	4		T3	3
valid_sources[0x39]	16267	1			T1	30		T2	8		T3	27
valid_sources[0x3a]	16096	1			T1	27		T2	9		T3	5
valid_sources[0x3b]	16040	1			T1	24		T2	8		T3	6
valid_sources[0x3c]	17023	1			T1	9		T2	2		T3	2
valid_sources[0x3d]	17656	1			T1	22		T2	10		T3	6
valid_sources[0x3e]	18138	1			T1	16		T2	10		T13	11
valid_sources[0x3f]	16358	1			T1	27		T2	4		T13	4
valid_sources[0x40]	16511	1			T1	21		T2	5		T3	8
valid_sources[0x41]	16894	1			T1	12		T2	13		T13	7
valid_sources[0x42]	16295	1			T1	28		T2	6		T3	6
valid_sources[0x43]	21613	1			T1	22		T2	8		T13	20
valid_sources[0x44]	16857	1			T1	18		T2	6		T3	12
valid_sources[0x45]	15715	1			T1	23		T2	8		T13	1
valid_sources[0x46]	43646	1			T1	23		T2	7		T3	1
valid_sources[0x47]	23924	1			T1	36		T2	6		T13	17
valid_sources[0x48]	16818	1			T1	15		T2	9		T13	10
valid_sources[0x49]	16600	1			T1	29		T2	8		T3	2
valid_sources[0x4a]	19793	1			T1	23		T2	5		T13	8
valid_sources[0x4b]	16819	1			T1	31		T2	12		T3	9
valid_sources[0x4c]	24303	1			T1	17		T2	10		T3	6
valid_sources[0x4d]	16578	1			T1	40		T2	9		T3	4
valid_sources[0x4e]	20865	1			T1	12		T2	5		T3	6
valid_sources[0x4f]	16219	1			T1	15		T2	12		T3	1
valid_sources[0x50]	16672	1			T1	42		T2	6		T3	1
valid_sources[0x51]	16104	1			T1	10		T2	11		T3	2
valid_sources[0x52]	20989	1			T1	23		T2	3		T3	1
valid_sources[0x53]	16048	1			T1	21		T2	4		T3	4
valid_sources[0x54]	16368	1			T1	31		T2	10		T3	3
valid_sources[0x55]	20537	1			T1	37		T2	6		T3	1
valid_sources[0x56]	16109	1			T1	14		T2	10		T3	14
valid_sources[0x57]	16869	1			T1	20		T2	9		T3	8
valid_sources[0x58]	34124	1			T1	6		T2	6		T3	2
valid_sources[0x59]	16252	1			T1	44		T2	8		T3	1
valid_sources[0x5a]	22315	1			T1	50		T2	1		T3	5
valid_sources[0x5b]	46527	1			T1	12		T2	8		T4	3237
valid_sources[0x5c]	22309	1			T1	20		T2	7		T3	1
valid_sources[0x5d]	17867	1			T1	29		T2	7		T14	37
valid_sources[0x5e]	16664	1			T1	38		T2	8		T3	11
valid_sources[0x5f]	16269	1			T1	11		T2	10		T3	6
valid_sources[0x60]	16518	1			T1	33		T2	11		T13	13
valid_sources[0x61]	53106	1			T1	15		T2	10		T13	15
valid_sources[0x62]	19406	1			T1	32		T2	15		T3	6
valid_sources[0x63]	32824	1			T1	25		T2	9		T13	10
valid_sources[0x64]	57320	1			T1	20		T2	7		T3	4
valid_sources[0x65]	16335	1			T1	10		T2	10		T3	6
valid_sources[0x66]	18788	1			T1	22		T2	7		T3	1
valid_sources[0x67]	16060	1			T1	13		T2	9		T3	2
valid_sources[0x68]	16343	1			T1	39		T2	8		T13	2
valid_sources[0x69]	15683	1			T1	14		T2	4		T3	3
valid_sources[0x6a]	15515	1			T1	10		T2	11		T13	3
valid_sources[0x6b]	15928	1			T1	47		T2	6		T3	1
valid_sources[0x6c]	15827	1			T1	12		T2	13		T3	1
valid_sources[0x6d]	15008	1			T1	23		T2	4		T13	5
valid_sources[0x6e]	17841	1			T1	41		T2	4		T3	10
valid_sources[0x6f]	22736	1			T1	40		T2	6		T3	7
valid_sources[0x70]	16205	1			T1	28		T2	18		T3	10
valid_sources[0x71]	16245	1			T1	16		T2	6		T3	6
valid_sources[0x72]	16249	1			T1	26		T2	6		T3	2
valid_sources[0x73]	16488	1			T1	21		T2	5		T3	4
valid_sources[0x74]	17337	1			T1	26		T2	8		T3	1
valid_sources[0x75]	19431	1			T1	21		T2	8		T3	16
valid_sources[0x76]	16560	1			T1	38		T2	16		T3	4
valid_sources[0x77]	16061	1			T1	35		T2	6		T3	6
valid_sources[0x78]	39758	1			T1	1		T2	13		T3	1
valid_sources[0x79]	25444	1			T1	26		T2	6		T13	8
valid_sources[0x7a]	18361	1			T1	19		T2	8		T3	2
valid_sources[0x7b]	17083	1			T1	25		T2	14		T3	6
valid_sources[0x7c]	16740	1			T1	17		T2	11		T13	5
valid_sources[0x7d]	16435	1			T1	17		T2	2		T3	8
valid_sources[0x7e]	16346	1			T1	23		T2	8		T3	3
valid_sources[0x7f]	17264	1			T1	11		T2	9		T13	5
valid_sources[0x80]	34551	1			T1	6		T2	6		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

328104

1

T1

118

T2

237

T3

306

values[0x0]

all_enables

biggest_size

144644

1

T1

17

T2

111

T3

75

values[0x1]

all_enables

biggest_size

130021

1

T1

9

T2

108

T3

77