Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3690093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

582155

1

T1

337

T2

157

T3

191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3880625	1			T1	3249		T2	874		T3	3611
values[0x0]	194151	1			T1	81		T2	35		T3	42
values[0x1]	197472	1			T1	67		T2	43		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2514399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1757849

1

T1

1315

T2

398

T3

1360

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14368	1			T1	15		T3	13		T4	3
valid_sources[0x01]	13113	1			T1	11		T3	20		T4	1
valid_sources[0x02]	29256	1			T1	12		T3	16		T4	2
valid_sources[0x03]	14762	1			T1	18		T3	12		T4	2
valid_sources[0x04]	14488	1			T1	18		T3	9		T5	24
valid_sources[0x05]	12882	1			T1	18		T3	18		T4	4
valid_sources[0x06]	15773	1			T1	14		T3	11		T5	20
valid_sources[0x07]	13908	1			T1	13		T3	9		T4	4
valid_sources[0x08]	13456	1			T1	13		T3	8		T4	4
valid_sources[0x09]	13569	1			T1	7		T3	8		T4	3
valid_sources[0x0a]	15603	1			T1	7		T3	17		T4	6
valid_sources[0x0b]	13397	1			T1	12		T3	17		T4	1
valid_sources[0x0c]	15868	1			T1	16		T3	10		T4	5
valid_sources[0x0d]	13788	1			T1	17		T3	16		T4	1
valid_sources[0x0e]	13729	1			T1	15		T3	16		T4	1
valid_sources[0x0f]	16932	1			T1	20		T3	9		T4	4
valid_sources[0x10]	14148	1			T1	14		T3	17		T4	7
valid_sources[0x11]	21129	1			T1	15		T3	16		T4	9
valid_sources[0x12]	15153	1			T1	14		T3	15		T4	5
valid_sources[0x13]	13500	1			T1	13		T3	14		T4	8
valid_sources[0x14]	13859	1			T1	13		T3	13		T4	1
valid_sources[0x15]	15314	1			T1	11		T3	21		T4	1
valid_sources[0x16]	13866	1			T1	17		T3	12		T4	6
valid_sources[0x17]	14531	1			T1	10		T3	19		T5	40
valid_sources[0x18]	18126	1			T1	14		T3	19		T4	2
valid_sources[0x19]	13245	1			T1	12		T3	18		T4	1
valid_sources[0x1a]	13371	1			T1	17		T3	17		T4	2
valid_sources[0x1b]	13926	1			T1	15		T3	14		T4	2
valid_sources[0x1c]	15966	1			T1	15		T3	14		T5	23
valid_sources[0x1d]	13952	1			T1	13		T3	24		T4	3
valid_sources[0x1e]	17052	1			T1	13		T3	13		T4	3
valid_sources[0x1f]	13135	1			T1	13		T3	9		T4	10
valid_sources[0x20]	15480	1			T1	11		T3	8		T4	10
valid_sources[0x21]	16627	1			T1	16		T3	10		T5	22
valid_sources[0x22]	19598	1			T1	16		T3	7		T4	3
valid_sources[0x23]	17186	1			T1	10		T3	14		T5	25
valid_sources[0x24]	12742	1			T1	13		T3	11		T4	3
valid_sources[0x25]	13282	1			T1	21		T3	20		T4	4
valid_sources[0x26]	13297	1			T1	15		T3	13		T5	28
valid_sources[0x27]	12756	1			T1	14		T3	19		T4	3
valid_sources[0x28]	16212	1			T1	18		T3	22		T4	1
valid_sources[0x29]	14303	1			T1	8		T3	22		T4	3
valid_sources[0x2a]	15682	1			T1	13		T3	12		T4	3
valid_sources[0x2b]	27349	1			T1	15		T3	18		T4	3
valid_sources[0x2c]	15863	1			T1	12		T3	17		T4	4
valid_sources[0x2d]	13403	1			T1	18		T3	20		T4	6
valid_sources[0x2e]	13731	1			T1	14		T3	10		T4	3
valid_sources[0x2f]	14000	1			T1	11		T3	16		T4	3
valid_sources[0x30]	13599	1			T1	15		T3	9		T4	2
valid_sources[0x31]	18056	1			T1	18		T3	16		T4	1
valid_sources[0x32]	13853	1			T1	9		T3	21		T4	5
valid_sources[0x33]	14892	1			T1	17		T3	15		T4	5
valid_sources[0x34]	14523	1			T1	17		T3	6		T4	1
valid_sources[0x35]	17267	1			T1	10		T3	13		T5	22
valid_sources[0x36]	33134	1			T1	7		T3	27		T4	3
valid_sources[0x37]	18984	1			T1	16		T3	23		T4	4
valid_sources[0x38]	13611	1			T1	13		T3	13		T4	2
valid_sources[0x39]	13497	1			T1	9		T3	14		T5	31
valid_sources[0x3a]	17588	1			T1	14		T3	13		T4	1
valid_sources[0x3b]	14302	1			T1	11		T3	16		T5	24
valid_sources[0x3c]	16770	1			T1	4		T3	10		T4	2
valid_sources[0x3d]	17165	1			T1	26		T3	15		T4	7
valid_sources[0x3e]	15506	1			T1	15		T3	17		T4	6
valid_sources[0x3f]	13499	1			T1	13		T3	12		T4	3
valid_sources[0x40]	13476	1			T1	11		T3	11		T4	2
valid_sources[0x41]	20590	1			T1	17		T3	14		T4	1
valid_sources[0x42]	14451	1			T1	17		T3	12		T4	3
valid_sources[0x43]	13548	1			T1	17		T3	14		T4	8
valid_sources[0x44]	13517	1			T1	6		T3	15		T4	11
valid_sources[0x45]	13277	1			T1	11		T3	19		T4	3
valid_sources[0x46]	13454	1			T1	15		T3	19		T4	2
valid_sources[0x47]	14899	1			T1	16		T3	14		T4	2
valid_sources[0x48]	15769	1			T1	20		T3	9		T4	2
valid_sources[0x49]	13584	1			T1	9		T3	14		T5	18
valid_sources[0x4a]	13876	1			T1	11		T3	19		T4	4
valid_sources[0x4b]	13072	1			T1	9		T3	20		T4	1
valid_sources[0x4c]	15331	1			T1	9		T3	17		T4	2
valid_sources[0x4d]	13204	1			T1	13		T3	10		T4	10
valid_sources[0x4e]	18474	1			T1	7		T3	17		T4	3
valid_sources[0x4f]	14363	1			T1	10		T3	16		T4	2
valid_sources[0x50]	13841	1			T1	11		T3	14		T4	2
valid_sources[0x51]	13242	1			T1	10		T3	17		T4	6
valid_sources[0x52]	13269	1			T1	9		T3	15		T5	41
valid_sources[0x53]	21905	1			T1	15		T3	7		T4	4
valid_sources[0x54]	13585	1			T1	12		T3	17		T4	3
valid_sources[0x55]	26390	1			T1	23		T3	16		T4	5
valid_sources[0x56]	17542	1			T1	16		T3	6		T4	1
valid_sources[0x57]	14892	1			T1	9		T3	13		T4	3
valid_sources[0x58]	23477	1			T1	10		T3	14		T4	1
valid_sources[0x59]	13295	1			T1	18		T3	14		T4	2
valid_sources[0x5a]	17891	1			T1	11		T3	17		T4	9
valid_sources[0x5b]	13458	1			T1	15		T3	14		T4	11
valid_sources[0x5c]	12996	1			T1	15		T3	12		T4	2
valid_sources[0x5d]	14522	1			T1	12		T3	11		T4	6
valid_sources[0x5e]	13390	1			T1	12		T3	14		T4	7
valid_sources[0x5f]	15043	1			T1	13		T3	16		T5	23
valid_sources[0x60]	14250	1			T1	13		T3	10		T4	1
valid_sources[0x61]	15051	1			T1	13		T3	17		T4	9
valid_sources[0x62]	13839	1			T1	14		T3	14		T4	2
valid_sources[0x63]	14049	1			T1	13		T3	23		T5	18
valid_sources[0x64]	18437	1			T1	13		T3	20		T5	31
valid_sources[0x65]	12809	1			T1	11		T3	15		T4	6
valid_sources[0x66]	13556	1			T1	12		T3	14		T5	30
valid_sources[0x67]	13959	1			T1	15		T3	18		T4	6
valid_sources[0x68]	14696	1			T1	21		T3	11		T4	4
valid_sources[0x69]	13873	1			T1	15		T3	18		T4	5
valid_sources[0x6a]	13145	1			T1	14		T3	16		T4	6
valid_sources[0x6b]	76394	1			T1	10		T3	14		T4	3
valid_sources[0x6c]	18145	1			T1	18		T3	9		T5	33
valid_sources[0x6d]	15031	1			T1	20		T3	12		T5	28
valid_sources[0x6e]	14714	1			T1	13		T3	16		T4	7
valid_sources[0x6f]	14506	1			T1	6		T3	11		T5	19
valid_sources[0x70]	17051	1			T1	15		T3	14		T4	5
valid_sources[0x71]	18896	1			T1	13		T3	8		T4	3
valid_sources[0x72]	14300	1			T1	14		T3	13		T4	3
valid_sources[0x73]	13998	1			T1	12		T3	20		T4	7
valid_sources[0x74]	24357	1			T1	13		T3	8		T4	2
valid_sources[0x75]	13924	1			T1	18		T3	15		T4	2
valid_sources[0x76]	21991	1			T1	15		T3	11		T4	10
valid_sources[0x77]	14159	1			T1	11		T3	22		T4	5
valid_sources[0x78]	13972	1			T1	8		T3	14		T4	4
valid_sources[0x79]	13378	1			T1	13		T3	6		T4	4
valid_sources[0x7a]	16241	1			T1	15		T3	9		T4	2
valid_sources[0x7b]	13351	1			T1	11		T3	21		T4	1
valid_sources[0x7c]	13411	1			T1	11		T3	11		T4	6
valid_sources[0x7d]	16848	1			T1	13		T3	13		T5	24
valid_sources[0x7e]	18862	1			T1	11		T3	19		T4	5
valid_sources[0x7f]	14714	1			T1	18		T3	13		T5	29
valid_sources[0x80]	20868	1			T1	22		T3	11		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

313949

1

T1

292

T2

134

T3

163

values[0x0]

all_enables

biggest_size

141092

1

T1

34

T2

17

T3

18

values[0x1]

all_enables

biggest_size

127114

1

T1

11

T2

6

T3

10