Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28089409	18104	0	0
attest_sw_binding_0_rd_A	28089409	1089	0	0
attest_sw_binding_1_rd_A	28089409	1060	0	0
attest_sw_binding_2_rd_A	28089409	1153	0	0
attest_sw_binding_3_rd_A	28089409	1018	0	0
attest_sw_binding_4_rd_A	28089409	1021	0	0
attest_sw_binding_5_rd_A	28089409	1141	0	0
attest_sw_binding_6_rd_A	28089409	1105	0	0
attest_sw_binding_7_rd_A	28089409	1082	0	0
intr_enable_rd_A	28089409	1545	0	0
key_version_rd_A	28089409	1135	0	0
max_creator_key_ver_regwen_rd_A	28089409	1091	0	0
max_owner_int_key_ver_regwen_rd_A	28089409	1029	0	0
max_owner_key_ver_regwen_rd_A	28089409	1100	0	0
reseed_interval_regwen_rd_A	28089409	998	0	0
salt_0_rd_A	28089409	1037	0	0
salt_1_rd_A	28089409	1052	0	0
salt_2_rd_A	28089409	1161	0	0
salt_3_rd_A	28089409	1153	0	0
salt_4_rd_A	28089409	1006	0	0
salt_5_rd_A	28089409	1009	0	0
salt_6_rd_A	28089409	1012	0	0
salt_7_rd_A	28089409	1035	0	0
sealing_sw_binding_0_rd_A	28089409	1054	0	0
sealing_sw_binding_1_rd_A	28089409	1026	0	0
sealing_sw_binding_2_rd_A	28089409	1106	0	0
sealing_sw_binding_3_rd_A	28089409	1082	0	0
sealing_sw_binding_4_rd_A	28089409	1160	0	0
sealing_sw_binding_5_rd_A	28089409	1012	0	0
sealing_sw_binding_6_rd_A	28089409	1071	0	0
sealing_sw_binding_7_rd_A	28089409	1071	0	0
sideload_clear_rd_A	28089409	1121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	18104	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	25	0	0
T102	23343	400	0	0
T103	0	20	0	0
T120	0	423	0	0
T127	0	351	0	0
T128	0	561	0	0
T129	0	158	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T164	0	5	0	0
T165	0	6	0	0
T166	0	6	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1089	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	45	0	0
T102	23343	0	0	0
T128	0	16	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	7	0	0
T168	0	7	0	0
T169	0	12	0	0
T170	0	13	0	0
T171	0	34	0	0
T172	0	1	0	0
T173	0	6	0	0
T174	0	28	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1060	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	62	0	0
T102	23343	0	0	0
T128	0	22	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	6	0	0
T168	0	5	0	0
T169	0	10	0	0
T170	0	12	0	0
T171	0	36	0	0
T172	0	11	0	0
T173	0	7	0	0
T174	0	19	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1153	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	68	0	0
T102	23343	0	0	0
T128	0	4	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	14	0	0
T170	0	15	0	0
T171	0	37	0	0
T172	0	1	0	0
T174	0	22	0	0
T175	0	27	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1018	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	69	0	0
T102	23343	0	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	10	0	0
T169	0	30	0	0
T171	0	16	0	0
T172	0	4	0	0
T173	0	9	0	0
T174	0	19	0	0
T175	0	36	0	0
T176	0	3	0	0
T177	0	7	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1021	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	63	0	0
T102	23343	0	0	0
T128	0	28	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T169	0	24	0	0
T171	0	26	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	20	0	0
T175	0	30	0	0
T176	0	3	0	0
T177	0	15	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1141	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	44	0	0
T102	23343	0	0	0
T128	0	14	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T168	0	3	0	0
T169	0	19	0	0
T170	0	9	0	0
T171	0	35	0	0
T172	0	4	0	0
T174	0	19	0	0
T175	0	42	0	0
T176	0	8	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1105	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	45	0	0
T102	23343	0	0	0
T128	0	12	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	9	0	0
T169	0	34	0	0
T170	0	4	0	0
T171	0	39	0	0
T172	0	10	0	0
T174	0	11	0	0
T175	0	24	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1082	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	55	0	0
T102	23343	0	0	0
T128	0	6	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	5	0	0
T169	0	27	0	0
T170	0	10	0	0
T171	0	27	0	0
T172	0	4	0	0
T174	0	16	0	0
T175	0	34	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1545	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T48	0	29	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	87	0	0
T102	23343	0	0	0
T128	0	12	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	7	0	0
T168	0	13	0	0
T169	0	6	0	0
T178	0	10	0	0
T179	0	25	0	0
T180	0	27	0	0
T181	0	17	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1135	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	44	0	0
T102	23343	0	0	0
T128	0	17	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	5	0	0
T168	0	6	0	0
T169	0	18	0	0
T170	0	9	0	0
T171	0	36	0	0
T172	0	4	0	0
T173	0	2	0	0
T174	0	16	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1091	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	68	0	0
T102	23343	0	0	0
T128	0	21	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T168	0	15	0	0
T169	0	22	0	0
T170	0	4	0	0
T171	0	19	0	0
T172	0	2	0	0
T173	0	6	0	0
T174	0	2	0	0
T175	0	34	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1029	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	39	0	0
T102	23343	0	0	0
T128	0	16	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	3	0	0
T168	0	5	0	0
T169	0	30	0	0
T170	0	12	0	0
T171	0	31	0	0
T172	0	9	0	0
T173	0	1	0	0
T174	0	28	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1100	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	51	0	0
T102	23343	0	0	0
T128	0	20	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	4	0	0
T168	0	7	0	0
T169	0	22	0	0
T171	0	18	0	0
T172	0	9	0	0
T173	0	5	0	0
T174	0	14	0	0
T175	0	39	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	998	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	58	0	0
T102	23343	0	0	0
T128	0	4	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	3	0	0
T170	0	11	0	0
T171	0	27	0	0
T172	0	1	0	0
T173	0	7	0	0
T174	0	13	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1037	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	51	0	0
T102	23343	0	0	0
T128	0	4	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	4	0	0
T170	0	4	0	0
T171	0	34	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	16	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1052	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	55	0	0
T102	23343	0	0	0
T128	0	17	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T168	0	10	0	0
T169	0	15	0	0
T171	0	48	0	0
T172	0	14	0	0
T173	0	10	0	0
T174	0	8	0	0
T175	0	26	0	0
T176	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1161	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	81	0	0
T102	23343	0	0	0
T128	0	17	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	24	0	0
T170	0	15	0	0
T171	0	24	0	0
T172	0	5	0	0
T173	0	1	0	0
T174	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1153	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	44	0	0
T102	23343	0	0	0
T128	0	3	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	6	0	0
T168	0	10	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	56	0	0
T172	0	1	0	0
T173	0	9	0	0
T174	0	23	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1006	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	43	0	0
T102	23343	0	0	0
T128	0	23	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	7	0	0
T169	0	20	0	0
T170	0	14	0	0
T171	0	46	0	0
T172	0	10	0	0
T174	0	24	0	0
T175	0	43	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1009	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	41	0	0
T102	23343	0	0	0
T128	0	19	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	6	0	0
T168	0	4	0	0
T169	0	14	0	0
T170	0	3	0	0
T171	0	34	0	0
T172	0	5	0	0
T173	0	1	0	0
T174	0	18	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1012	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	62	0	0
T102	23343	0	0	0
T128	0	2	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	3	0	0
T168	0	3	0	0
T169	0	12	0	0
T171	0	29	0	0
T172	0	8	0	0
T173	0	6	0	0
T174	0	12	0	0
T175	0	28	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1035	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	37	0	0
T102	23343	0	0	0
T128	0	6	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	3	0	0
T168	0	12	0	0
T169	0	18	0	0
T170	0	9	0	0
T171	0	33	0	0
T172	0	2	0	0
T174	0	19	0	0
T175	0	15	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1054	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	41	0	0
T102	23343	0	0	0
T128	0	1	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	4	0	0
T168	0	6	0	0
T169	0	23	0	0
T170	0	24	0	0
T171	0	41	0	0
T172	0	4	0	0
T173	0	2	0	0
T174	0	12	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1026	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	33	0	0
T102	23343	0	0	0
T128	0	8	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	4	0	0
T168	0	9	0	0
T169	0	22	0	0
T170	0	12	0	0
T171	0	37	0	0
T172	0	10	0	0
T173	0	2	0	0
T174	0	15	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1106	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	67	0	0
T102	23343	0	0	0
T128	0	16	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	5	0	0
T168	0	10	0	0
T169	0	13	0	0
T170	0	13	0	0
T171	0	22	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	9	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1082	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	57	0	0
T102	23343	0	0	0
T128	0	13	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	7	0	0
T169	0	8	0	0
T170	0	1	0	0
T171	0	33	0	0
T172	0	3	0	0
T173	0	9	0	0
T174	0	8	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1160	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	56	0	0
T102	23343	0	0	0
T128	0	19	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	3	0	0
T168	0	6	0	0
T169	0	20	0	0
T170	0	8	0	0
T171	0	27	0	0
T172	0	6	0	0
T173	0	5	0	0
T174	0	15	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1012	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	56	0	0
T102	23343	0	0	0
T128	0	11	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	7	0	0
T169	0	5	0	0
T170	0	8	0	0
T171	0	37	0	0
T172	0	2	0	0
T173	0	7	0	0
T174	0	19	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1071	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	59	0	0
T102	23343	0	0	0
T128	0	10	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	5	0	0
T168	0	4	0	0
T169	0	1	0	0
T170	0	8	0	0
T171	0	40	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1071	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	64	0	0
T102	23343	0	0	0
T128	0	15	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T167	0	1	0	0
T168	0	2	0	0
T169	0	22	0	0
T170	0	3	0	0
T171	0	15	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	17	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28089409	1121	0	0
T24	14537	0	0	0
T29	29869	0	0	0
T31	8688	0	0	0
T32	10365	0	0	0
T51	3780	0	0	0
T58	16878	0	0	0
T101	14888	45	0	0
T102	23343	0	0	0
T128	0	17	0	0
T131	22847	0	0	0
T132	11059	0	0	0
T168	0	2	0	0
T169	0	21	0	0
T170	0	3	0	0
T171	0	36	0	0
T172	0	4	0	0
T173	0	9	0	0
T174	0	14	0	0
T175	0	31	0	0