Module Definition
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Module : keymgr_kmac_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.14 100.00 90.91 54.55 95.24 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_kmac_if 97.23 100.00 90.91 100.00 95.24 100.00



Module Instance : tb.dut.u_kmac_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.23 100.00 90.91 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : keymgr_kmac_if
Line No.TotalCoveredPercent
TOTAL111111100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
ALWAYS15733100.00
ALWAYS16533100.00
ALWAYS1685656100.00
CONT_ASSIGN28311100.00
ALWAYS29188100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN31111100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31811100.00
ALWAYS32099100.00
CONT_ASSIGN33211100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34711100.00
ALWAYS35344100.00
CONT_ASSIGN35911100.00
CONT_ASSIGN36511100.00
ALWAYS36977100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
130 1 1
131 1 1
132 1 1
134 1 1
157 1 1
158 1 1
160 1 1
165 3 3
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
178 1 1
179 1 1
180 1 1
182 1 1
184 1 1
186 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
==> MISSING_ELSE
204 1 1
MISSING_ELSE
209 1 1
210 1 1
213 1 1
214 1 1
217 1 1
218 1 1
MISSING_ELSE
MISSING_ELSE
225 1 1
226 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
237 1 1
238 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
MISSING_ELSE
252 1 1
253 1 1
256 1 1
257 1 1
258 1 1
259 1 1
MISSING_ELSE
275 1 1
276 1 1
277 1 1
278 1 1
MISSING_ELSE
283 1 1
291 1 1
293 1 1
294 1 1
295 1 1
296 1 1
298 1 1
300 1 1
302 1 1
MISSING_ELSE
308 1 1
311 1 1
312 1 1
313 1 1
318 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
MISSING_ELSE
332 1 1
333 1 1
334 1 1
339 1 1
341 1 1
346 1 1
347 1 1
353 1 1
354 1 1
355 1 1
356 1 1
MISSING_ELSE
359 1 1
365 1 1
369 1 1
370 1 1
371 1 1
372 1 1
374 1 1
375 1 1
376 1 1
381 1 1
384 1 1


Cond Coverage for Module : keymgr_kmac_if
TotalCoveredPercent
Conditions777090.91
Logical777090.91
Non-Logical00
Event00

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       204
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       204
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       217
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------
-1-StatusTests
0CoveredT3,T4,T15
1CoveredT1,T2,T3

 LINE       283
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       283
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--
-1--2-StatusTests
01CoveredT12,T20,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       296
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT1,T2,T3
11CoveredT25,T26,T27

 LINE       296
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT25,T26,T27

 LINE       298
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT27,T28,T29
10CoveredT2,T4,T5
11Not Covered

 LINE       298
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT27,T28,T29

 LINE       300
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT4,T5,T30

 LINE       300
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T4,T5

 LINE       302
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT4,T5,T30

 LINE       302
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T4,T5

 LINE       321
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT12,T13,T14
010CoveredT4,T5,T30
100CoveredT31,T32,T33

 LINE       323
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       325
 EXPRESSION (valid && id_en_i)
             --1--    ---2---
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       327
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T34,T21
11CoveredT1,T2,T3

 LINE       339
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T36,T37
10CoveredT1,T2,T3

 LINE       339
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       359
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33

 LINE       359
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT31,T32,T33

 LINE       359
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       365
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33

 LINE       381
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T20,T34
10CoveredT31,T22,T38

 LINE       384
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T15
11CoveredT1,T2,T3

FSM Coverage for Module : keymgr_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 6 54.55
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StClean 247 Covered T1,T2,T3
StError 276 Covered T12,T13,T14
StIdle 259 Covered T1,T2,T3
StOpWait 238 Covered T1,T2,T3
StTx 204 Covered T1,T2,T3
StTxLast 204 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StClean->StError 276 Not Covered
StClean->StIdle 259 Covered T1,T2,T3
StIdle->StError 276 Covered T12,T13,T14
StIdle->StTx 204 Covered T1,T2,T3
StIdle->StTxLast 204 Not Covered
StOpWait->StClean 247 Covered T1,T2,T3
StOpWait->StError 276 Not Covered
StTx->StError 276 Not Covered
StTx->StTxLast 218 Covered T1,T2,T3
StTxLast->StError 276 Not Covered
StTxLast->StOpWait 238 Covered T1,T2,T3



Branch Coverage for Module : keymgr_kmac_if
Line No.TotalCoveredPercent
Branches 42 40 95.24
TERNARY 283 2 2 100.00
IF 157 2 2 100.00
IF 165 2 2 100.00
CASE 186 21 19 90.48
IF 275 2 2 100.00
IF 293 3 3 100.00
IF 321 5 5 100.00
IF 353 3 3 100.00
IF 369 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 283 ((start && done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 194 if (start) -3-: 196 if (adv_en_i) -4-: 198 if (id_en_i) -5-: 200 if (gen_en_i) -6-: 204 ((rounds == 5'b0)) ? -7-: 213 if (kmac_data_i.ready) -8-: 217 if ((cnt == 5'(1'b1))) -9-: 228 if (adv_en_i) -10-: 230 if (id_en_i) -11-: 232 if (gen_en_i) -12-: 238 (kmac_data_i.ready) ? -13-: 244 if (kmac_data_i.done) -14-: 256 if ((!start))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 1 - - - - - - - - - - Covered T2,T4,T5
StIdle 1 0 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 0 0 - - - - - - - - - Not Covered
StIdle 1 - - - 1 - - - - - - - - Not Covered
StIdle 1 - - - 0 - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StTx - - - - - 1 1 - - - - - - Covered T1,T2,T3
StTx - - - - - 1 0 - - - - - - Covered T1,T2,T3
StTx - - - - - 0 - - - - - - - Covered T3,T4,T15
StTxLast - - - - - - - 1 - - - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 1 - - - - Covered T2,T4,T5
StTxLast - - - - - - - 0 0 1 - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 0 0 - - - Covered T20,T21,T39
StTxLast - - - - - - - - - - 1 - - Covered T1,T2,T3
StTxLast - - - - - - - - - - 0 - - Covered T3,T4,T15
StOpWait - - - - - - - - - - - 1 - Covered T1,T2,T3
StOpWait - - - - - - - - - - - 0 - Covered T1,T2,T3
StClean - - - - - - - - - - - - 1 Covered T1,T2,T3
StClean - - - - - - - - - - - - 0 Covered T21
default - - - - - - - - - - - - - Covered T12,T13,T14


LineNo. Expression -1-: 275 if (cnt_err)

Branches:
-1-StatusTests
1 Covered T12,T13,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 if (clr_err) -2-: 295 if (valid)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 321 if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o)) -2-: 323 if ((valid && adv_en_i)) -3-: 325 if ((valid && id_en_i)) -4-: 327 if ((valid && gen_en_i))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T4,T5,T30
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T4,T5
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 353 if ((!rst_ni)) -2-: 355 if (cnt_set)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : keymgr_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AdvRemBytes_A 895 895 0 0
GenRemBytes_A 895 895 0 0
IdRemBytes_A 895 895 0 0
LastStrb_A 34439256 26520750 0 0
u_state_regs_A 35202661 35027933 0 0


AdvRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GenRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

IdRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

LastStrb_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34439256 26520750 0 0
T1 4738 468 0 0
T2 4273 332 0 0
T3 25784 20873 0 0
T4 25089 13433 0 0
T5 3746 462 0 0
T15 7266 1808 0 0
T16 6117 468 0 0
T17 3658 468 0 0
T18 146230 135566 0 0
T19 9753 3967 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 35027933 0 0
T1 4738 4675 0 0
T2 4273 4203 0 0
T3 25784 25722 0 0
T4 25089 25036 0 0
T5 3746 3662 0 0
T15 7266 7198 0 0
T16 6117 6038 0 0
T17 3658 3560 0 0
T18 146230 146138 0 0
T19 9753 9662 0 0

Line Coverage for Instance : tb.dut.u_kmac_if
Line No.TotalCoveredPercent
TOTAL111111100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
ALWAYS15733100.00
ALWAYS16533100.00
ALWAYS1685656100.00
CONT_ASSIGN28311100.00
ALWAYS29188100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN31111100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31811100.00
ALWAYS32099100.00
CONT_ASSIGN33211100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN33411100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34711100.00
ALWAYS35344100.00
CONT_ASSIGN35911100.00
CONT_ASSIGN36511100.00
ALWAYS36977100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
130 1 1
131 1 1
132 1 1
134 1 1
157 1 1
158 1 1
160 1 1
165 3 3
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
178 1 1
179 1 1
180 1 1
182 1 1
184 1 1
186 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
==> MISSING_ELSE
204 1 1
MISSING_ELSE
209 1 1
210 1 1
213 1 1
214 1 1
217 1 1
218 1 1
MISSING_ELSE
MISSING_ELSE
225 1 1
226 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
237 1 1
238 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
MISSING_ELSE
252 1 1
253 1 1
256 1 1
257 1 1
258 1 1
259 1 1
MISSING_ELSE
275 1 1
276 1 1
277 1 1
278 1 1
MISSING_ELSE
283 1 1
291 1 1
293 1 1
294 1 1
295 1 1
296 1 1
298 1 1
300 1 1
302 1 1
MISSING_ELSE
308 1 1
311 1 1
312 1 1
313 1 1
318 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
MISSING_ELSE
332 1 1
333 1 1
334 1 1
339 1 1
341 1 1
346 1 1
347 1 1
353 1 1
354 1 1
355 1 1
356 1 1
MISSING_ELSE
359 1 1
365 1 1
369 1 1
370 1 1
371 1 1
372 1 1
374 1 1
375 1 1
376 1 1
381 1 1
384 1 1


Cond Coverage for Instance : tb.dut.u_kmac_if
TotalCoveredPercent
Conditions777090.91
Logical777090.91
Non-Logical00
Event00

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       204
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       204
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       217
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------
-1-StatusTests
0CoveredT3,T4,T15
1CoveredT1,T2,T3

 LINE       283
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       283
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--
-1--2-StatusTests
01CoveredT12,T20,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       296
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT22,T23,T24
10CoveredT1,T2,T3
11CoveredT25,T26,T27

 LINE       296
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT25,T26,T27

 LINE       298
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT27,T28,T29
10CoveredT2,T4,T5
11Not Covered

 LINE       298
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT27,T28,T29

 LINE       300
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT4,T5,T30

 LINE       300
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T4,T5

 LINE       302
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT4,T5,T30

 LINE       302
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T4,T5

 LINE       321
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT12,T13,T14
010CoveredT4,T5,T30
100CoveredT31,T32,T33

 LINE       323
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       325
 EXPRESSION (valid && id_en_i)
             --1--    ---2---
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       327
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T34,T21
11CoveredT1,T2,T3

 LINE       339
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T36,T37
10CoveredT1,T2,T3

 LINE       339
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       359
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33

 LINE       359
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT31,T32,T33

 LINE       359
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       365
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33

 LINE       381
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T20,T34
10CoveredT31,T22,T38

 LINE       384
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T15
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_kmac_if
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StClean 247 Covered T1,T2,T3
StError 276 Covered T12,T13,T14
StIdle 259 Covered T1,T2,T3
StOpWait 238 Covered T1,T2,T3
StTx 204 Covered T1,T2,T3
StTxLast 204 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StClean->StError 276 Excluded
StClean->StIdle 259 Covered T1,T2,T3
StIdle->StError 276 Covered T12,T13,T14
StIdle->StTx 204 Covered T1,T2,T3
StIdle->StTxLast 204 Excluded
StOpWait->StClean 247 Covered T1,T2,T3
StOpWait->StError 276 Excluded
StTx->StError 276 Excluded
StTx->StTxLast 218 Covered T1,T2,T3
StTxLast->StError 276 Excluded
StTxLast->StOpWait 238 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_kmac_if
Line No.TotalCoveredPercent
Branches 42 40 95.24
TERNARY 283 2 2 100.00
IF 157 2 2 100.00
IF 165 2 2 100.00
CASE 186 21 19 90.48
IF 275 2 2 100.00
IF 293 3 3 100.00
IF 321 5 5 100.00
IF 353 3 3 100.00
IF 369 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 283 ((start && done_o)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 186 case (state_q) -2-: 194 if (start) -3-: 196 if (adv_en_i) -4-: 198 if (id_en_i) -5-: 200 if (gen_en_i) -6-: 204 ((rounds == 5'b0)) ? -7-: 213 if (kmac_data_i.ready) -8-: 217 if ((cnt == 5'(1'b1))) -9-: 228 if (adv_en_i) -10-: 230 if (id_en_i) -11-: 232 if (gen_en_i) -12-: 238 (kmac_data_i.ready) ? -13-: 244 if (kmac_data_i.done) -14-: 256 if ((!start))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 1 - - - - - - - - - - Covered T2,T4,T5
StIdle 1 0 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle 1 0 0 0 - - - - - - - - - Not Covered
StIdle 1 - - - 1 - - - - - - - - Not Covered
StIdle 1 - - - 0 - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StTx - - - - - 1 1 - - - - - - Covered T1,T2,T3
StTx - - - - - 1 0 - - - - - - Covered T1,T2,T3
StTx - - - - - 0 - - - - - - - Covered T3,T4,T15
StTxLast - - - - - - - 1 - - - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 1 - - - - Covered T2,T4,T5
StTxLast - - - - - - - 0 0 1 - - - Covered T1,T2,T3
StTxLast - - - - - - - 0 0 0 - - - Covered T20,T21,T39
StTxLast - - - - - - - - - - 1 - - Covered T1,T2,T3
StTxLast - - - - - - - - - - 0 - - Covered T3,T4,T15
StOpWait - - - - - - - - - - - 1 - Covered T1,T2,T3
StOpWait - - - - - - - - - - - 0 - Covered T1,T2,T3
StClean - - - - - - - - - - - - 1 Covered T1,T2,T3
StClean - - - - - - - - - - - - 0 Covered T21
default - - - - - - - - - - - - - Covered T12,T13,T14


LineNo. Expression -1-: 275 if (cnt_err)

Branches:
-1-StatusTests
1 Covered T12,T13,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 if (clr_err) -2-: 295 if (valid)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 321 if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o)) -2-: 323 if ((valid && adv_en_i)) -3-: 325 if ((valid && id_en_i)) -4-: 327 if ((valid && gen_en_i))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T4,T5,T30
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T2,T4,T5
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 353 if ((!rst_ni)) -2-: 355 if (cnt_set)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_kmac_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AdvRemBytes_A 895 895 0 0
GenRemBytes_A 895 895 0 0
IdRemBytes_A 895 895 0 0
LastStrb_A 34439256 26520750 0 0
u_state_regs_A 35202661 35027933 0 0


AdvRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

GenRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

IdRemBytes_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 895 895 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

LastStrb_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34439256 26520750 0 0
T1 4738 468 0 0
T2 4273 332 0 0
T3 25784 20873 0 0
T4 25089 13433 0 0
T5 3746 462 0 0
T15 7266 1808 0 0
T16 6117 468 0 0
T17 3658 468 0 0
T18 146230 135566 0 0
T19 9753 3967 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35202661 35027933 0 0
T1 4738 4675 0 0
T2 4273 4203 0 0
T3 25784 25722 0 0
T4 25089 25036 0 0
T5 3746 3662 0 0
T15 7266 7198 0 0
T16 6117 6038 0 0
T17 3658 3560 0 0
T18 146230 146138 0 0
T19 9753 9662 0 0