Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	96.15	98.39	99.96		95.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.08	96.15	98.39	99.96		95.92	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	96.15	98.39	99.96		95.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	99.10	97.79	98.64	100.00	99.20	98.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	98.15	100.00	94.44			100.00
u_checks	100.00	100.00					100.00
u_ctrl	97.17	99.70	95.19	95.40	100.00	98.62	94.12
u_fault_alert	100.00			100.00
u_intr_op_done	100.00	100.00	100.00			100.00	100.00
u_kmac_if	97.73	100.00	90.91	100.00	100.00	95.45	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_op_err_alert	100.00			100.00
u_reg	99.44	98.86	98.75	100.00		99.61	100.00
u_reseed_ctrl	98.36	100.00	91.80	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	98.87	100.00	94.34		100.00	100.00	100.00
u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
TOTAL		78	75	96.15
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
ALWAYS	425	3	3	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	467	1	0	0.00
CONT_ASSIGN	468	1	0	0.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	672	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
ALWAYS	715	5	5	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	773	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
237	1	1
238	1	1
240	1	1
241	1	1
274	2	2
278	1	1
328	1	1
330	1	1
348	1	1
355	1	1
371	1	1
401	1	1
406	1	1
419	1	1
421	1	1
425	1	1
426	1	1
427	1	1
430	1	1
437	1	1
450	1	1
452	1	1
454	1	1
455	1	1
458	1	1
463	1	1
466	0	1
467	0	1
468	0	1
476	1	1
477	1	1
480	1	1
482	1	1
492	1	1
493	1	1
494	1	1
497	1	1
532	1	1
533	1	1
534	1	1
535	1	1
536	1	1
537	1	1
538	1	1
539	1	1
546	1	1
547	1	1
548	1	1
549	1	1
664	1	1
665	1	1
666	1	1
668	1	1
669	1	1
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
705	1	1
707	1	1
710	1	1
711	1	1
715	1	1
716	1	1
717	1	1
719	1	1
720	1	1
725	1	1
742	1	1
773		unreachable

---

Cond Coverage for Module : keymgr

	Total	Covered	Percent
Conditions	186	183	98.39
Logical	186	183	98.39
Non-Logical	0	0
Event	0	0

 LINE       217
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       217
 EXPRESSION (seed_en & ((~reg2hw.start.q)))
             ---1---   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       338
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       355
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T2,T4,T5

 LINE       371
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       401
 EXPRESSION ((cdi_sel == 1'b0) ? reg2hw.sealing_sw_binding : ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       401
 SUB-EXPRESSION (cdi_sel == 1'b0)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       401
 SUB-EXPRESSION ((cdi_sel == 1'b1) ? reg2hw.attest_sw_binding : RndCnstCdi)
                 --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       401
 SUB-EXPRESSION (cdi_sel == 1'b1)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       437
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T27,T89,T90
1	0	1	1	Covered	T28,T91,T92
1	1	0	1	Covered	T25,T26,T93
1	1	1	0	Covered	T41,T86,T26
1	1	1	1	Covered	T1,T2,T3

 LINE       477
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       477
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       477
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T17

 LINE       477
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T17

 LINE       477
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       477
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       482
 EXPRESSION (invalid_stage_sel ? ({GenLfsrCopies {lfsr[31:0]}}) : ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       532
 EXPRESSION (adv_en | id_en | gen_en)
             ---1--   --2--   ---3--

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T4,T5
1	0	0	Covered	T1,T2,T3

 LINE       533
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~creator_seed_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T93,T91,T89
1	0	1	Covered	T27,T94,T95
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T93,T91,T89

 LINE       533
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       534
 EXPRESSION (adv_en & (stage_sel == OwnerInt) & ((~owner_seed_vld)))
             ---1--   -----------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T96,T97
1	0	1	Covered	T98,T28,T93
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T23,T97

 LINE       534
 SUB-EXPRESSION (stage_sel == OwnerInt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       535
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~devid_vld)))
             ---1--   -----------2----------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T93,T91
1	0	1	Covered	T94,T95,T23
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T28,T93,T91

 LINE       535
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~health_state_vld)))
             ---1--   -----------2----------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T25,T26,T28
1	0	1	Covered	T25,T94,T95
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T25,T26,T28

 LINE       536
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       537
 EXPRESSION (gen_en & ((~key_version_vld)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T30

 LINE       538
 EXPRESSION (valid_op & ((~key_vld)))
             ----1---   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T29

 LINE       539
 EXPRESSION (adv_en & (stage_sel == Creator) & ((~rom_digest_vld)))
             ---1--   -----------2----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T28,T93
1	0	1	Covered	T86,T26,T99
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T26,T28,T93

 LINE       539
 SUB-EXPRESSION (stage_sel == Creator)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       546
 EXPRESSION (((~key_vld)) | ((~adv_dvalid[stage_sel])))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T26,T90
1	0	Covered	T1,T2,T3

 LINE       548
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       617
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       617
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       624
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T7,T37,T27
1	0	Covered	T1,T2,T3

 LINE       707
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T35,T36

 LINE       707
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       711
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       711
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       725
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T100,T101,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T100,T101,T102

 LINE       742
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T100,T101,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T100,T101,T102

---

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	69	67	97.10
Total Bits	10582	10578	99.96
Total Bits 0->1	5291	5289	99.96
Total Bits 1->0	5291	5289	99.96

Ports	69	67	97.10
Port Bits	10582	10578	99.96
Port Bits 0->1	5291	5289	99.96
Port Bits 1->0	5291	5289	99.96

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T41,T35,T103	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T41,T35,T103	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T41,T35,T103	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T104	Yes	T1,T2,T104	INPUT
tl_i.a_user.rsvd[9:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T103,T40,T42	Yes	T103,T40,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.valid	Yes	Yes	T2,T3,T15	Yes	T2,T3,T15	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_key_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.key[1:0][383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otbn_key_o.valid	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	OUTPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	Yes	Yes	T41,T27,T29	Yes	T41,T40,T42	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T3,T4,T15	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T103,T6,T50	Yes	T2,T16,T17	INPUT
lc_keymgr_div_i[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otp_key_i.owner_seed_valid	Yes	Yes	T103,T6,T7	Yes	T35,T103,T6	INPUT
otp_key_i.owner_seed[255:0]	Yes	Yes	T6,T50,T60	Yes	T6,T50,T60	INPUT
otp_key_i.creator_seed_valid	Yes	Yes	T103,T6,T50	Yes	T103,T6,T50	INPUT
otp_key_i.creator_seed[255:0]	Yes	Yes	T6,T50,T60	Yes	T6,T50,T7	INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T6,T50,T60	Yes	T6,T50,T36	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T103,T6,T50	Yes	T35,T103,T6	INPUT
otp_device_id_i[255:0]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][1]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][4:3]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][5]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][6]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][7]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][8]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][9]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][10]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][11]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][12]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][13]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][15:14]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][16]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][17]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][18]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][21:20]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][22]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][25:23]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][26]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][27]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][28]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][29]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][30]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][31]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][32]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][33]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][34]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][35]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][36]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][39:38]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][40]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][41]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][42]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][43]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][44]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][46:45]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][47]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][48]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][49]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][50]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][51]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][52]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][53]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][54]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][55]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][56]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][57]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][60:58]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][61]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][62]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][65:63]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][66]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][67]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][69:68]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][70]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][71]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][72]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][73]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][74]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][75]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][76]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][77]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][78]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][79]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][80]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][81]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][82]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][83]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][84]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][85]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][86]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][87]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][88]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][89]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][90]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][91]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][93:92]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][94]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][96:95]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][97]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][99:98]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][100]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][101]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][102]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][103]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][104]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][105]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][106]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][108:107]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][109]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][110]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][111]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][112]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][113]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][114]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][115]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][116]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][117]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][118]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][119]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][120]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][121]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][122]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][123]	Yes	Yes	T5,T18,T19	Yes	T5,T18,T19	INPUT
flash_i.seeds[0][124]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][125]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][126]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][127]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][129:128]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][131:130]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][133:132]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][136:134]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][137]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][138]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][139]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][140]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][141]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][142]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][144:143]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][145]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][147:146]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][149:148]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][150]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][151]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][152]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][153]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][154]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][155]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][156]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][157]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][158]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][159]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][160]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][161]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][163:162]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][164]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][165]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][166]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][167]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][168]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][169]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][170]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][171]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][173:172]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][174]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][175]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][177:176]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][178]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][179]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][180]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][181]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][182]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][183]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][184]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][185]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][186]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][187]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][188]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][189]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][190]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][191]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][192]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][193]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][195:194]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][196]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][197]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][198]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][199]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][200]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][202:201]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][203]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][204]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][205]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][207:206]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][208]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][209]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][210]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][211]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][212]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][213]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][214]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][215]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[0][216]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][217]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][218]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][219]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][220]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][222:221]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][223]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][224]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][225]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][226]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][227]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][230:228]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][231]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][232]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[0][233]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][234]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][235]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][236]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][237]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][238]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][239]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][241:240]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][242]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][243]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][244]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[0][245]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][246]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][248:247]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][249]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[0][254:250]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[0][255]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][1]	Yes	Yes	T4,T18,T19	Yes	T4,T18,T19	INPUT
flash_i.seeds[1][2]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][3]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][4]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][5]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][6]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][7]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][8]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][9]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][10]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][11]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][12]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][13]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][16:14]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][17]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][18]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][19]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][20]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][23:21]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][24]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][26:25]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][27]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][28]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][29]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][30]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][32:31]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][33]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][34]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][35]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][36]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][37]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][38]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][39]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][40]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][43:41]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][44]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][45]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][46]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][47]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][48]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][49]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][50]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][51]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][52]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][53]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][55:54]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][56]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][57]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][58]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][60:59]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][61]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][62]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][63]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][64]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][66:65]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][67]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][68]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][69]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][70]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][71]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][72]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][75:73]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][77:76]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][78]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][79]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][80]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][81]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][82]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][83]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][85:84]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][86]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][88:87]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][89]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][90]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][91]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][92]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][93]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][94]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][95]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][96]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][97]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][98]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][99]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][100]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][101]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][102]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][103]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][104]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][105]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][106]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][107]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][108]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][111:109]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][112]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][113]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][114]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][115]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][116]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][117]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][118]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][119]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][120]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][121]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][122]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][124:123]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][125]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][126]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][127]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][128]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][129]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][131:130]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][132]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][133]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][136:134]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][137]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][138]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][139]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][140]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][142:141]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][143]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][144]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][145]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][147:146]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][149:148]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][150]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][151]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][155:152]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][156]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][157]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][158]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][159]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][160]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][161]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][162]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][163]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][164]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][165]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][166]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][167]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][169:168]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][170]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][172:171]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][173]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][174]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][175]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][176]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][177]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][178]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][179]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][182:180]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][183]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][184]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][185]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][186]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][187]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][188]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][189]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][190]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][191]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][192]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][195:193]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][196]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][198:197]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][199]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][200]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][201]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][202]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][203]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][204]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][205]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][206]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][207]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][209:208]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][211:210]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][212]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][213]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][214]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][215]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][217:216]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][218]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][219]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][220]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][222:221]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][223]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][226:224]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][229:227]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][230]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][231]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][232]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][233]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][234]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][235]	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
flash_i.seeds[1][236]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][237]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][238]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][240:239]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][241]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][242]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][243]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][244]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][245]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][246]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][247]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][248]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
flash_i.seeds[1][250:249]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][251]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][252]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][254:253]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_i.seeds[1][255]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T3	Yes	T1,T3,T15	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i[0].valid	Yes	Yes	T41,T86,T28	Yes	T41,T86,T28	INPUT
rom_digest_i[0].data[255:0]	Yes	Yes	T2,T4,T5	Yes	T4,T18,T19	INPUT
rom_digest_i[1].valid	Yes	Yes	T41,T26,T28	Yes	T41,T28,T89	INPUT
rom_digest_i[1].data[255:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
intr_op_done_o	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T41,T35,T100	Yes	T41,T35,T100	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T41,T35,T100	Yes	T41,T35,T100	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr

	Line No.	Total	Covered	Percent
Branches		49	47	95.92
TERNARY	401	3	2	66.67
TERNARY	477	4	4	100.00
TERNARY	482	2	2	100.00
TERNARY	707	3	2	66.67
TERNARY	711	3	3	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	624	2	2	100.00
IF	715	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	401	((cdi_sel == 1'b0)) ? 
-2-:	401	((cdi_sel == 1'b1)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	477	((dest_sel == Aes)) ? 
-2-:	477	((dest_sel == Kmac)) ? 
-3-:	477	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T2,T4,T17
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	(invalid_stage_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	707	(fault_errs) ? 
-2-:	707	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T41,T35,T36
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	711	(op_errs) ? 
-2-:	711	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	617	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	624	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	715	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	27	27	100.00	27	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	27	27	100.00	27	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	895	895	0	0
AesKeyKnownO_A	35202661	35027933	0	0
AlertKnownO_A	35202661	35027933	0	0
ErrCntMatch_A	895	895	0	0
FaultCntMatch_A	895	895	0	0
FpvSecCmCtrlCntAlertCheck_A	35202661	80	0	0
FpvSecCmCtrlDataFsmCheck_A	35202661	80	0	0
FpvSecCmCtrlMainFsmCheck_A	35202661	80	0	0
FpvSecCmCtrlOpFsmCheck_A	35202661	80	0	0
FpvSecCmKmacIfCntAlertCheck_A	35202661	80	0	0
FpvSecCmKmacIfFsmCheck_A	35202661	80	0	0
FpvSecCmRegWeOnehotCheck_A	35202661	80	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	35202661	80	0	0
FpvSecCmSideloadCtrlFsmCheck_A	35202661	80	0	0
GenDataWidth_A	895	895	0	0
IdDataWidth_A	895	895	0	0
IntrKnownO_A	35202661	35027933	0	0
KmacDataKnownO_A	34439256	34268401	0	0
KmacKeyKnownO_A	35202661	35027933	0	0
KmacMaskCheck_A	895	895	0	0
LfsrWidth_A	895	895	0	0
MaxWidthDivisible_A	895	895	0	0
OtbnKeyKnownO_A	35202661	35027933	0	0
OutputKeyDiff_A	895	895	0	0
StageMatch_A	895	895	0	0
TlAReadyKnownO_A	35202661	35027933	0	0
TlDValidKnownO_A	35202661	35027933	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	80	0	0
T12	127745	20	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	10247	0	0	0
T47	0	20	0	0
T73	7901	0	0	0
T90	23785	0	0	0
T105	0	10	0	0
T106	2453	0	0	0
T107	2124	0	0	0
T108	10141	0	0	0
T109	119208	0	0	0
T110	8174	0	0	0
T111	20278	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IdDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34439256	34268401	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

MaxWidthDivisible_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

StageMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	895	895	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35202661	35027933	0	0
T1	4738	4675	0	0
T2	4273	4203	0	0
T3	25784	25722	0	0
T4	25089	25036	0	0
T5	3746	3662	0	0
T15	7266	7198	0	0
T16	6117	6038	0	0
T17	3658	3560	0	0
T18	146230	146138	0	0
T19	9753	9662	0	0