Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	36969818	22223	0	0
attest_sw_binding_0_rd_A	36969818	1044	0	0
attest_sw_binding_1_rd_A	36969818	1136	0	0
attest_sw_binding_2_rd_A	36969818	1082	0	0
attest_sw_binding_3_rd_A	36969818	1157	0	0
attest_sw_binding_4_rd_A	36969818	1118	0	0
attest_sw_binding_5_rd_A	36969818	1076	0	0
attest_sw_binding_6_rd_A	36969818	1029	0	0
attest_sw_binding_7_rd_A	36969818	1093	0	0
intr_enable_rd_A	36969818	1932	0	0
key_version_rd_A	36969818	1113	0	0
max_creator_key_ver_regwen_rd_A	36969818	975	0	0
max_owner_int_key_ver_regwen_rd_A	36969818	1189	0	0
max_owner_key_ver_regwen_rd_A	36969818	1046	0	0
reseed_interval_regwen_rd_A	36969818	1146	0	0
salt_0_rd_A	36969818	1034	0	0
salt_1_rd_A	36969818	1015	0	0
salt_2_rd_A	36969818	1077	0	0
salt_3_rd_A	36969818	1104	0	0
salt_4_rd_A	36969818	1014	0	0
salt_5_rd_A	36969818	967	0	0
salt_6_rd_A	36969818	1116	0	0
salt_7_rd_A	36969818	1103	0	0
sealing_sw_binding_0_rd_A	36969818	1037	0	0
sealing_sw_binding_1_rd_A	36969818	1082	0	0
sealing_sw_binding_2_rd_A	36969818	1143	0	0
sealing_sw_binding_3_rd_A	36969818	1009	0	0
sealing_sw_binding_4_rd_A	36969818	1124	0	0
sealing_sw_binding_5_rd_A	36969818	1054	0	0
sealing_sw_binding_6_rd_A	36969818	1089	0	0
sealing_sw_binding_7_rd_A	36969818	1102	0	0
sideload_clear_rd_A	36969818	1114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	22223	0	0
T57	8217	0	0	0
T79	2750	0	0	0
T103	7371	407	0	0
T112	27836	1445	0	0
T113	18134	29	0	0
T119	37015	0	0	0
T122	0	639	0	0
T123	0	591	0	0
T124	0	278	0	0
T125	0	37	0	0
T126	0	380	0	0
T127	0	43	0	0
T128	0	145	0	0
T129	59135	0	0	0
T130	7610	0	0	0
T131	2403	0	0	0
T132	8717	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1044	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	58	0	0
T116	0	15	0	0
T117	0	48	0	0
T120	0	41	0	0
T122	15262	0	0	0
T125	0	22	0	0
T139	0	4	0	0
T182	0	8	0	0
T183	0	216	0	0
T184	0	11	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1136	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	65	0	0
T116	0	21	0	0
T117	0	35	0	0
T120	0	16	0	0
T122	15262	0	0	0
T125	0	30	0	0
T182	0	2	0	0
T183	0	344	0	0
T184	0	7	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	4	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1082	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	45	0	0
T116	0	17	0	0
T117	0	32	0	0
T120	0	23	0	0
T122	15262	0	0	0
T125	0	14	0	0
T139	0	3	0	0
T182	0	6	0	0
T183	0	235	0	0
T184	0	12	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1157	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	63	0	0
T116	0	17	0	0
T117	0	34	0	0
T120	0	38	0	0
T122	15262	0	0	0
T125	0	20	0	0
T182	0	9	0	0
T183	0	334	0	0
T184	0	10	0	0
T185	0	4	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	2	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1118	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	48	0	0
T116	0	7	0	0
T117	0	38	0	0
T120	0	22	0	0
T122	15262	0	0	0
T125	0	25	0	0
T182	0	8	0	0
T183	0	318	0	0
T184	0	24	0	0
T185	0	9	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	1	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1076	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	79	0	0
T116	0	11	0	0
T117	0	52	0	0
T120	0	42	0	0
T122	15262	0	0	0
T125	0	35	0	0
T139	0	8	0	0
T182	0	9	0	0
T183	0	220	0	0
T184	0	11	0	0
T185	0	8	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1029	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	46	0	0
T116	0	7	0	0
T117	0	14	0	0
T120	0	30	0	0
T122	15262	0	0	0
T125	0	29	0	0
T182	0	8	0	0
T183	0	245	0	0
T184	0	20	0	0
T185	0	1	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	1	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1093	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	47	0	0
T116	0	12	0	0
T117	0	32	0	0
T120	0	15	0	0
T122	15262	0	0	0
T125	0	23	0	0
T139	0	2	0	0
T182	0	12	0	0
T183	0	289	0	0
T184	0	11	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1932	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	38	0	0
T116	0	4	0	0
T117	0	37	0	0
T122	15262	0	0	0
T125	0	48	0	0
T182	0	12	0	0
T183	0	230	0	0
T184	0	1	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	6	0	0
T193	0	24	0	0
T194	0	20	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1113	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	45	0	0
T116	0	6	0	0
T117	0	34	0	0
T120	0	44	0	0
T122	15262	0	0	0
T125	0	16	0	0
T139	0	2	0	0
T182	0	4	0	0
T183	0	273	0	0
T184	0	10	0	0
T185	0	2	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	975	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	60	0	0
T116	0	13	0	0
T117	0	38	0	0
T120	0	28	0	0
T122	15262	0	0	0
T125	0	10	0	0
T139	0	3	0	0
T183	0	266	0	0
T184	0	14	0	0
T185	0	3	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	7	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1189	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	42	0	0
T116	0	1	0	0
T117	0	31	0	0
T120	0	37	0	0
T122	15262	0	0	0
T125	0	20	0	0
T139	0	5	0	0
T182	0	8	0	0
T183	0	286	0	0
T184	0	18	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	4	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1046	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	68	0	0
T116	0	10	0	0
T117	0	36	0	0
T120	0	42	0	0
T122	15262	0	0	0
T125	0	26	0	0
T182	0	13	0	0
T183	0	235	0	0
T184	0	18	0	0
T185	0	2	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	10	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1146	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	64	0	0
T116	0	21	0	0
T117	0	32	0	0
T120	0	18	0	0
T122	15262	0	0	0
T125	0	20	0	0
T139	0	9	0	0
T183	0	230	0	0
T184	0	8	0	0
T185	0	2	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1034	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	37	0	0
T116	0	13	0	0
T117	0	34	0	0
T120	0	35	0	0
T122	15262	0	0	0
T125	0	15	0	0
T139	0	3	0	0
T182	0	2	0	0
T183	0	307	0	0
T184	0	17	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1015	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	63	0	0
T116	0	4	0	0
T117	0	38	0	0
T120	0	33	0	0
T122	15262	0	0	0
T125	0	29	0	0
T139	0	1	0	0
T182	0	5	0	0
T183	0	227	0	0
T184	0	14	0	0
T185	0	1	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1077	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	54	0	0
T116	0	12	0	0
T117	0	34	0	0
T120	0	48	0	0
T122	15262	0	0	0
T125	0	36	0	0
T139	0	8	0	0
T182	0	16	0	0
T183	0	250	0	0
T184	0	14	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	3	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1104	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	57	0	0
T116	0	16	0	0
T117	0	33	0	0
T120	0	22	0	0
T122	15262	0	0	0
T125	0	23	0	0
T182	0	7	0	0
T183	0	291	0	0
T184	0	10	0	0
T185	0	5	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1014	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	39	0	0
T116	0	13	0	0
T117	0	35	0	0
T120	0	36	0	0
T122	15262	0	0	0
T125	0	14	0	0
T183	0	196	0	0
T184	0	3	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	3	0	0
T195	0	86	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	967	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	49	0	0
T116	0	12	0	0
T117	0	35	0	0
T120	0	37	0	0
T122	15262	0	0	0
T125	0	26	0	0
T183	0	187	0	0
T184	0	11	0	0
T185	0	10	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	9	0	0
T195	0	76	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1116	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	54	0	0
T116	0	9	0	0
T117	0	38	0	0
T120	0	11	0	0
T122	15262	0	0	0
T125	0	35	0	0
T182	0	9	0	0
T183	0	250	0	0
T184	0	10	0	0
T185	0	3	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	9	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1103	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	66	0	0
T116	0	16	0	0
T117	0	25	0	0
T120	0	27	0	0
T122	15262	0	0	0
T125	0	16	0	0
T182	0	17	0	0
T183	0	265	0	0
T184	0	10	0	0
T185	0	4	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	1	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1037	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	53	0	0
T116	0	7	0	0
T117	0	35	0	0
T120	0	34	0	0
T122	15262	0	0	0
T125	0	21	0	0
T182	0	12	0	0
T183	0	253	0	0
T184	0	5	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	14	0	0
T195	0	89	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1082	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	78	0	0
T116	0	7	0	0
T117	0	25	0	0
T120	0	35	0	0
T122	15262	0	0	0
T125	0	11	0	0
T139	0	4	0	0
T182	0	3	0	0
T183	0	237	0	0
T184	0	14	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1143	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	74	0	0
T116	0	9	0	0
T117	0	32	0	0
T120	0	32	0	0
T122	15262	0	0	0
T125	0	41	0	0
T139	0	7	0	0
T182	0	13	0	0
T183	0	272	0	0
T184	0	18	0	0
T185	0	2	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1009	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	78	0	0
T116	0	16	0	0
T117	0	44	0	0
T120	0	31	0	0
T122	15262	0	0	0
T125	0	31	0	0
T182	0	4	0	0
T183	0	243	0	0
T184	0	14	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	3	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1124	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	58	0	0
T116	0	4	0	0
T117	0	30	0	0
T120	0	28	0	0
T122	15262	0	0	0
T125	0	15	0	0
T183	0	236	0	0
T184	0	22	0	0
T185	0	1	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	19	0	0
T192	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1054	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	45	0	0
T116	0	17	0	0
T117	0	30	0	0
T120	0	24	0	0
T122	15262	0	0	0
T125	0	28	0	0
T183	0	250	0	0
T184	0	14	0	0
T185	0	3	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	19	0	0
T192	0	6	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1089	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	58	0	0
T116	0	11	0	0
T117	0	48	0	0
T120	0	23	0	0
T122	15262	0	0	0
T125	0	21	0	0
T139	0	3	0	0
T182	0	12	0	0
T183	0	274	0	0
T184	0	4	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T192	0	3	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1102	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	64	0	0
T116	0	8	0	0
T117	0	51	0	0
T120	0	21	0	0
T122	15262	0	0	0
T125	0	28	0	0
T183	0	244	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	23	0	0
T195	0	92	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36969818	1114	0	0
T43	39096	0	0	0
T46	13747	0	0	0
T79	2750	0	0	0
T113	18134	58	0	0
T116	0	15	0	0
T117	0	45	0	0
T120	0	27	0	0
T122	15262	0	0	0
T125	0	27	0	0
T183	0	278	0	0
T184	0	10	0	0
T185	0	6	0	0
T186	1184	0	0	0
T187	4169	0	0	0
T188	253254	0	0	0
T189	20417	0	0	0
T190	23564	0	0	0
T191	0	2	0	0
T195	0	70	0	0