Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : keymgr_sideload_key_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sideload_ctrl 100.00 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sideload_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.87 100.00 94.34 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.09 96.20 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_aes_key 95.83 100.00 87.50 100.00
u_kmac_key 95.83 100.00 87.50 100.00
u_mubi_buf 100.00 100.00 100.00
u_otbn_key 95.83 100.00 87.50 100.00
u_state_regs 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_sideload_key_ctrl
Line No.TotalCoveredPercent
TOTAL5050100.00
ALWAYS6533100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8811100.00
ALWAYS911313100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
ALWAYS19266100.00
ALWAYS19266100.00
ALWAYS19266100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 3 3
70 2 2
77 1 1
83 1 1
84 1 1
85 1 1
88 1 1
91 1 1
92 1 1
93 1 1
95 1 1
97 1 1
98 1 1
MISSING_ELSE
105 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
MISSING_ELSE
120 1 1
143 1 1
144 1 1
145 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
MISSING_ELSE
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
MISSING_ELSE
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
MISSING_ELSE
204 1 1
205 1 1
206 1 1
213 1 1
216 1 1
219 1 1

Cond Coverage for Module : keymgr_sideload_key_ctrl
TotalCoveredPercent
Conditions2929100.00
Logical2929100.00
Non-Logical00
Event00

 LINE       77
 EXPRESSION (wipe_key_i | ((!(clr_key_i inside {SideLoadClrIdle, SideLoadClrAes, SideLoadClrKmac, SideLoadClrOtbn}))))
             -----1----   ---------------------------------------------2---------------------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT13,T21,T69 

 LINE       83
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrAes))
             ------1-----   --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T17
10CoveredT1,T2,T4 

 LINE       83
 SUB-EXPRESSION (clr_key_i == SideLoadClrAes)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T17 

 LINE       84
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrKmac))
             ------1-----   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T12
10CoveredT1,T2,T4 

 LINE       84
 SUB-EXPRESSION (clr_key_i == SideLoadClrKmac)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T12 

 LINE       85
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrOtbn))
             ------1-----   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T14
10CoveredT1,T2,T4 

 LINE       85
 SUB-EXPRESSION (clr_key_i == SideLoadClrOtbn)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T14 

 LINE       147
 EXPRESSION (data_valid_i & slot_sel[AesIdx])
             ------1-----   --------2-------
-1--2-StatusTests
01CoveredT4,T12,T14
10CoveredT1,T2,T3
11CoveredT4,T12,T14 

 LINE       162
 EXPRESSION (data_valid_i & slot_sel[OtbnIdx])
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT2,T12,T16
10CoveredT1,T2,T3
11CoveredT2,T12,T16 

 LINE       176
 EXPRESSION (data_valid_i & slot_sel[KmacIdx])
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4 

 LINE       216
 EXPRESSION (key_i.valid ? key_i : kmac_sideload_key)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
FSM Coverage for Module : keymgr_sideload_key_ctrl
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 3 3 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StSideloadIdle 98 Covered T1,T2,T3
StSideloadReset 96 Covered T1,T2,T3
StSideloadStop 114 Covered T13,T21,T34
StSideloadWipe 107 Covered T13,T21,T34


transitions   Line No.   Covered   Tests   
StSideloadIdle->StSideloadWipe 107 Covered T13,T21,T34
StSideloadReset->StSideloadIdle 98 Covered T1,T2,T3
StSideloadWipe->StSideloadStop 114 Covered T13,T21,T34


Branch Coverage for Module : keymgr_sideload_key_ctrl
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 216 2 2 100.00
IF 65 2 2 100.00
CASE 95 8 8 100.00
IF 192 4 4 100.00
IF 192 4 4 100.00
IF 192 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	216	(key_i.valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	65	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	95	case (state_q)
-2-:	97	if (init_i)
-3-:	106	if (wipe_key_i)
-4-:	113	if ((!wipe_key_i))

Branches:
-1--2--3--4-StatusTests
StSideloadReset 1 - - Covered T1,T2,T3
StSideloadReset 0 - - Covered T1,T2,T3
StSideloadIdle - 1 - Covered T13,T21,T34
StSideloadIdle - 0 - Covered T1,T2,T3
StSideloadWipe - - 1 Covered T13,T21,T34
StSideloadWipe - - 0 Covered T21,T34,T44
StSideloadStop - - - Covered T13,T21,T34
default - - - Covered T5,T7,T11 



	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[0])
-3-:	196	if (slot_sel[0])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T4
0 0 1 Covered T14,T15,T40
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[1])
-3-:	196	if (slot_sel[1])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T13
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	192	if ((!rst_ni))
-2-:	194	if (slot_clr[2])
-3-:	196	if (slot_sel[2])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T4
0 0 1 Covered T17,T40,T41
0 0 0 Covered T1,T2,T3

Assert Coverage for Module : keymgr_sideload_key_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
KmacKeySource_a 26913013 10531 0 0
u_state_regs_A 27074175 26924788 0 0


KmacKeySource_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 26913013 10531 0 0
T1 4101 9 0 0
T2 2707 12 0 0
T3 7813 7 0 0
T4 2556 15 0 0
T12 8517 11 0 0
T13 11036 1 0 0
T14 8330 7 0 0
T15 5177 7 0 0
T16 9958 3 0 0
T17 17910 7 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27074175 26924788 0 0
T1 4101 4042 0 0
T2 2707 2651 0 0
T3 7813 7735 0 0
T4 2556 2486 0 0
T12 8517 8421 0 0
T13 11036 10869 0 0
T14 8330 8235 0 0
T15 5177 5096 0 0
T16 9958 9870 0 0
T17 17910 17852 0 0