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Module Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_share1_output_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_working_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_working_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_op_status.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_op_status


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_invalid_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_invalid_kmac_input


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_invalid_shadow_update


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_kmac_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_kmac_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_kmac_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.67 100.00 50.00 80.00 u_fault_status_kmac_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_regfile_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_shadow


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_ctrl_fsm_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb
tb.dut.u_reg.u_working_state.wr_en_data_arb
tb.dut.u_reg.u_op_status.wr_en_data_arb
tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb
tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb
tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb
tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb
tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb
tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb
tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb
tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb
tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb
tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
154 1 1
158 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
154 1 1
158 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
154 1 1
158 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
154 1 1
158 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
154 1 1
158 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_working_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN39100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 0 1
40 1 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_op_status.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_op_status.wr_en_data_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT147,T139,T140
Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T21,T25
10CoveredT1,T2,T3 

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT12,T21,T26
11CoveredT12,T21,T25 

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T25 

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T123,T119
10CoveredT1,T2,T3 

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT122,T123,T119 

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT122,T123,T119 

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1