Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_working_state.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb	66.67	66.67
tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb	95.00	100.00	90.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_start.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sideload_clear.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_salt_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_version.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_op_status.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_op_status.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb

SCORE	LINE
95.00	100.00

tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	102	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
102	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_start.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sideload_clear.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_salt_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_version.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	37	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
37	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	127	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
127	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=6,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	158	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
154	1	1
158		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_working_state.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_cmd.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_kmac_fsm.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_kmac_done.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_kmac_op.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_kmac_out.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_regfile_intg.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_shadow.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_ctrl_fsm_intg.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb

SCORE	LINE
66.67	66.67

tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	45	0	0
CONT_ASSIGN	46	0	0
CONT_ASSIGN	47	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
45		unreachable
46		unreachable
47	1	1

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=6,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share0_output_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sw_share1_output_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_op_status.wr_en_data_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_operation.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sideload_clear.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_op.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_err_code_invalid_kmac_input.wr_en_data_arb

SCORE	COND
95.00	90.00

tb.dut.u_reg.u_err_code_invalid_shadow_update.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_start.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_cdi_sel.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_shadowed.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_reseed_interval_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       105
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T22
1	0	Covered	T1,T2,T4

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T21,T22

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_sealing_sw_binding_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_attest_sw_binding_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_salt_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_version.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_creator_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_int_key_ver_shadowed.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_max_owner_key_ver_shadowed.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_control_shadowed_dest_sel.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3