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Module Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_ctrl_fsm_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_ctrl_fsm_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_reseed_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_side_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_side_ctrl_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_fault_status_key_ecc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_creator_seed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_owner_seed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_dev_id


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_health_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_key_version


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_key


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_debug_invalid_digest


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb
tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb
tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb
tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb
tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb
tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_chk.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_ctrl_fsm_cnt.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_reseed_cnt.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_fsm.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_side_ctrl_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_key_ecc.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_creator_seed.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT23,T97,T98
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T97,T98
11CoveredT23,T97,T98 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T97,T98 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_owner_seed.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT20,T101
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T101
11CoveredT20,T101 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T101 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_dev_id.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T95
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T95
11CoveredT22,T23,T95 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T95 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_health_state.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T102
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T102
11CoveredT22,T23,T102 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T102 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key_version.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T21,T25
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT12,T21,T26
11CoveredT12,T21,T25 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T25 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_key.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T22,T24
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T22,T24
11CoveredT21,T22,T24 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T24 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26
Line Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_debug_invalid_digest.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T23,T95
10CoveredT12,T21,T26 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT22,T23,T95
11CoveredT22,T23,T95 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T23,T95 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T21,T26