Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.09	96.20	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28715200	19936	0	0
attest_sw_binding_0_rd_A	28715200	1029	0	0
attest_sw_binding_1_rd_A	28715200	1010	0	0
attest_sw_binding_2_rd_A	28715200	997	0	0
attest_sw_binding_3_rd_A	28715200	1154	0	0
attest_sw_binding_4_rd_A	28715200	1051	0	0
attest_sw_binding_5_rd_A	28715200	1090	0	0
attest_sw_binding_6_rd_A	28715200	1048	0	0
attest_sw_binding_7_rd_A	28715200	1077	0	0
intr_enable_rd_A	28715200	1674	0	0
key_version_rd_A	28715200	1064	0	0
max_creator_key_ver_regwen_rd_A	28715200	1040	0	0
max_owner_int_key_ver_regwen_rd_A	28715200	1140	0	0
max_owner_key_ver_regwen_rd_A	28715200	1070	0	0
reseed_interval_regwen_rd_A	28715200	1077	0	0
salt_0_rd_A	28715200	1154	0	0
salt_1_rd_A	28715200	1118	0	0
salt_2_rd_A	28715200	1053	0	0
salt_3_rd_A	28715200	1094	0	0
salt_4_rd_A	28715200	1053	0	0
salt_5_rd_A	28715200	1061	0	0
salt_6_rd_A	28715200	1064	0	0
salt_7_rd_A	28715200	1135	0	0
sealing_sw_binding_0_rd_A	28715200	978	0	0
sealing_sw_binding_1_rd_A	28715200	1067	0	0
sealing_sw_binding_2_rd_A	28715200	1111	0	0
sealing_sw_binding_3_rd_A	28715200	1179	0	0
sealing_sw_binding_4_rd_A	28715200	1016	0	0
sealing_sw_binding_5_rd_A	28715200	994	0	0
sealing_sw_binding_6_rd_A	28715200	1175	0	0
sealing_sw_binding_7_rd_A	28715200	992	0	0
sideload_clear_rd_A	28715200	1060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	19936	0	0
T22	17018	0	0	0
T36	8456	0	0	0
T56	54505	0	0	0
T106	17548	242	0	0
T107	26318	1317	0	0
T109	11410	619	0	0
T128	0	159	0	0
T129	0	455	0	0
T130	0	78	0	0
T131	0	109	0	0
T132	0	623	0	0
T135	949	0	0	0
T136	9635	0	0	0
T137	4287	0	0	0
T138	24303	0	0	0
T139	0	1	0	0
T177	0	7	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1029	0	0
T119	17825	32	0	0
T122	17827	20	0	0
T123	22621	86	0	0
T125	0	41	0	0
T129	11429	12	0	0
T134	11189	2	0	0
T147	3241	11	0	0
T148	6255	46	0	0
T170	20309	0	0	0
T176	0	30	0	0
T178	1828	5	0	0
T179	796	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1010	0	0
T119	17825	32	0	0
T121	22257	0	0	0
T122	17827	17	0	0
T123	22621	69	0	0
T125	0	38	0	0
T129	11429	1	0	0
T147	3241	8	0	0
T148	6255	9	0	0
T170	20309	0	0	0
T176	0	25	0	0
T178	1828	10	0	0
T179	796	0	0	0
T180	0	5	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	997	0	0
T119	17825	37	0	0
T121	22257	0	0	0
T122	17827	22	0	0
T123	22621	62	0	0
T125	0	25	0	0
T134	11189	3	0	0
T147	3241	4	0	0
T148	6255	28	0	0
T170	20309	0	0	0
T176	0	42	0	0
T178	1828	9	0	0
T179	796	0	0	0
T180	0	4	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1154	0	0
T119	17825	25	0	0
T122	17827	23	0	0
T123	22621	65	0	0
T125	0	33	0	0
T129	11429	8	0	0
T134	11189	12	0	0
T147	3241	5	0	0
T148	6255	32	0	0
T170	20309	0	0	0
T176	0	67	0	0
T178	1828	5	0	0
T179	796	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1051	0	0
T119	17825	25	0	0
T121	22257	0	0	0
T122	17827	28	0	0
T123	22621	72	0	0
T125	0	22	0	0
T147	3241	16	0	0
T148	6255	33	0	0
T170	20309	0	0	0
T176	18789	26	0	0
T178	1828	3	0	0
T179	796	0	0	0
T180	0	4	0	0
T181	0	14	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1090	0	0
T119	17825	57	0	0
T122	17827	20	0	0
T123	22621	91	0	0
T125	0	33	0	0
T129	11429	10	0	0
T134	11189	1	0	0
T147	3241	6	0	0
T148	6255	15	0	0
T170	20309	0	0	0
T176	0	32	0	0
T178	1828	5	0	0
T179	796	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1048	0	0
T119	17825	20	0	0
T122	17827	30	0	0
T123	22621	60	0	0
T125	0	36	0	0
T129	11429	7	0	0
T134	11189	7	0	0
T147	3241	5	0	0
T148	6255	33	0	0
T170	20309	0	0	0
T176	0	32	0	0
T178	1828	5	0	0
T179	796	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1077	0	0
T119	17825	37	0	0
T122	17827	32	0	0
T123	22621	61	0	0
T125	0	24	0	0
T129	11429	10	0	0
T134	11189	2	0	0
T147	3241	11	0	0
T148	6255	7	0	0
T170	20309	0	0	0
T176	0	47	0	0
T178	1828	4	0	0
T179	796	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1674	0	0
T119	17825	44	0	0
T122	17827	40	0	0
T123	22621	81	0	0
T134	11189	8	0	0
T147	3241	9	0	0
T148	6255	34	0	0
T178	1828	6	0	0
T182	861	4	0	0
T183	1106	5	0	0
T184	1578	10	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1064	0	0
T119	17825	60	0	0
T121	22257	0	0	0
T122	17827	25	0	0
T123	22621	66	0	0
T125	0	18	0	0
T134	11189	1	0	0
T147	3241	9	0	0
T148	6255	39	0	0
T170	20309	0	0	0
T176	0	52	0	0
T178	1828	8	0	0
T179	796	0	0	0
T185	0	62	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1040	0	0
T119	17825	50	0	0
T121	22257	0	0	0
T122	17827	28	0	0
T123	22621	75	0	0
T125	0	24	0	0
T134	11189	4	0	0
T147	3241	9	0	0
T148	6255	28	0	0
T170	20309	0	0	0
T176	0	35	0	0
T178	1828	2	0	0
T179	796	0	0	0
T181	0	1	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1140	0	0
T119	17825	45	0	0
T121	22257	0	0	0
T122	17827	27	0	0
T123	22621	53	0	0
T125	0	34	0	0
T129	11429	3	0	0
T147	3241	12	0	0
T148	6255	5	0	0
T170	20309	0	0	0
T176	0	38	0	0
T178	1828	5	0	0
T179	796	0	0	0
T180	0	3	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1070	0	0
T119	17825	38	0	0
T122	17827	31	0	0
T123	22621	56	0	0
T125	0	36	0	0
T129	11429	2	0	0
T134	11189	16	0	0
T147	3241	8	0	0
T148	6255	31	0	0
T170	20309	0	0	0
T176	0	20	0	0
T178	1828	3	0	0
T179	796	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1077	0	0
T119	17825	40	0	0
T122	17827	26	0	0
T123	22621	55	0	0
T125	0	32	0	0
T129	11429	10	0	0
T134	11189	2	0	0
T147	3241	12	0	0
T148	6255	17	0	0
T170	20309	0	0	0
T176	0	50	0	0
T178	1828	4	0	0
T179	796	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1154	0	0
T119	17825	32	0	0
T122	17827	27	0	0
T123	22621	86	0	0
T125	0	35	0	0
T129	11429	22	0	0
T134	11189	2	0	0
T147	3241	9	0	0
T148	6255	33	0	0
T170	20309	0	0	0
T176	0	40	0	0
T178	1828	1	0	0
T179	796	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1118	0	0
T119	17825	38	0	0
T121	22257	0	0	0
T122	17827	21	0	0
T123	22621	84	0	0
T125	0	17	0	0
T134	11189	25	0	0
T147	3241	11	0	0
T148	6255	17	0	0
T170	20309	0	0	0
T176	0	41	0	0
T178	1828	1	0	0
T179	796	0	0	0
T180	0	7	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1053	0	0
T119	17825	49	0	0
T121	22257	0	0	0
T122	17827	20	0	0
T123	22621	63	0	0
T125	0	26	0	0
T134	11189	12	0	0
T147	3241	12	0	0
T148	6255	11	0	0
T170	20309	0	0	0
T176	0	38	0	0
T178	1828	5	0	0
T179	796	0	0	0
T180	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1094	0	0
T119	17825	27	0	0
T122	17827	30	0	0
T123	22621	89	0	0
T125	0	21	0	0
T129	11429	6	0	0
T134	11189	8	0	0
T147	3241	4	0	0
T148	6255	39	0	0
T170	20309	0	0	0
T176	0	21	0	0
T178	1828	5	0	0
T179	796	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1053	0	0
T119	17825	6	0	0
T121	22257	0	0	0
T122	17827	34	0	0
T123	22621	79	0	0
T125	0	26	0	0
T134	11189	6	0	0
T147	3241	15	0	0
T148	6255	29	0	0
T170	20309	0	0	0
T176	0	36	0	0
T178	1828	3	0	0
T179	796	0	0	0
T180	0	11	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1061	0	0
T119	17825	28	0	0
T122	17827	32	0	0
T123	22621	86	0	0
T125	0	21	0	0
T129	11429	5	0	0
T134	11189	8	0	0
T147	3241	12	0	0
T148	6255	7	0	0
T170	20309	0	0	0
T176	0	33	0	0
T178	1828	1	0	0
T179	796	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1064	0	0
T119	17825	49	0	0
T121	22257	0	0	0
T122	17827	24	0	0
T123	22621	68	0	0
T125	0	26	0	0
T129	11429	3	0	0
T147	3241	13	0	0
T148	6255	25	0	0
T170	20309	0	0	0
T176	0	40	0	0
T178	1828	5	0	0
T179	796	0	0	0
T180	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1135	0	0
T119	17825	24	0	0
T122	17827	40	0	0
T123	22621	73	0	0
T125	0	32	0	0
T129	11429	3	0	0
T134	11189	13	0	0
T147	3241	11	0	0
T148	6255	43	0	0
T170	20309	0	0	0
T176	0	35	0	0
T178	1828	5	0	0
T179	796	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	978	0	0
T119	17825	25	0	0
T121	22257	0	0	0
T122	17827	30	0	0
T123	22621	75	0	0
T125	0	31	0	0
T129	11429	7	0	0
T147	3241	11	0	0
T148	6255	12	0	0
T170	20309	0	0	0
T176	0	31	0	0
T178	1828	3	0	0
T179	796	0	0	0
T180	0	5	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1067	0	0
T119	17825	49	0	0
T122	17827	37	0	0
T123	22621	75	0	0
T125	0	23	0	0
T129	11429	9	0	0
T134	11189	1	0	0
T147	3241	6	0	0
T148	6255	14	0	0
T170	20309	0	0	0
T176	0	26	0	0
T178	1828	3	0	0
T179	796	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1111	0	0
T119	17825	39	0	0
T122	17827	20	0	0
T123	22621	63	0	0
T125	0	31	0	0
T129	11429	13	0	0
T134	11189	12	0	0
T147	3241	7	0	0
T148	6255	6	0	0
T170	20309	0	0	0
T176	0	24	0	0
T178	1828	2	0	0
T179	796	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1179	0	0
T119	17825	67	0	0
T122	17827	22	0	0
T123	22621	70	0	0
T125	0	24	0	0
T129	11429	2	0	0
T134	11189	13	0	0
T147	3241	11	0	0
T148	6255	25	0	0
T170	20309	0	0	0
T176	0	18	0	0
T178	1828	5	0	0
T179	796	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1016	0	0
T119	17825	35	0	0
T121	22257	0	0	0
T122	17827	34	0	0
T123	22621	69	0	0
T125	0	26	0	0
T134	11189	8	0	0
T147	3241	4	0	0
T148	6255	32	0	0
T170	20309	0	0	0
T176	0	24	0	0
T178	1828	0	0	0
T179	796	0	0	0
T180	0	9	0	0
T181	0	5	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	994	0	0
T119	17825	27	0	0
T121	22257	0	0	0
T122	17827	20	0	0
T123	22621	85	0	0
T125	0	28	0	0
T134	11189	4	0	0
T147	3241	13	0	0
T148	6255	23	0	0
T170	20309	0	0	0
T176	0	33	0	0
T178	1828	6	0	0
T179	796	0	0	0
T180	0	1	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1175	0	0
T119	17825	29	0	0
T122	17827	28	0	0
T123	22621	79	0	0
T125	0	25	0	0
T129	11429	11	0	0
T134	11189	2	0	0
T147	3241	6	0	0
T148	6255	3	0	0
T170	20309	0	0	0
T176	0	37	0	0
T178	1828	0	0	0
T179	796	0	0	0
T181	0	9	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	992	0	0
T119	17825	12	0	0
T121	22257	0	0	0
T122	17827	13	0	0
T123	22621	52	0	0
T125	0	29	0	0
T134	11189	20	0	0
T147	3241	7	0	0
T148	6255	35	0	0
T170	20309	0	0	0
T176	0	36	0	0
T178	1828	2	0	0
T179	796	0	0	0
T181	0	7	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28715200	1060	0	0
T119	17825	32	0	0
T121	22257	0	0	0
T122	17827	26	0	0
T123	22621	96	0	0
T125	0	33	0	0
T134	11189	15	0	0
T147	3241	4	0	0
T148	6255	26	0	0
T170	20309	0	0	0
T176	0	38	0	0
T178	1828	9	0	0
T179	796	0	0	0
T180	0	6	0	0