Unified Coverage Report :: Module :: keymgr_dpe_op_state_ctrl

Module : keymgr_dpe_op_state_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.78	85.29	66.67		50.00	76.92	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_op_state	75.78	85.29	66.67		50.00	76.92	100.00

---

Module Instance : tb.dut.u_ctrl.u_op_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.78	85.29	66.67		50.00	76.92	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.01	88.37	66.67		50.00	80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.76	89.84	77.44		46.15	79.66	85.71	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_op_state_ctrl

	Line No.	Total	Covered	Percent
TOTAL		34	29	85.29
ALWAYS	68	3	3	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	74	30	25	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	3	3
71	1	1
74	1	1
75	1	1
76	1	1
77	1	1
80	1	1
82	1	1
83	1	1
85	1	1
87	1	1
88	0	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	0	1
			MISSING_ELSE
104	0	1
105	0	1
106	0	1
110	1	1
111	1	1
113	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
122	1	1
123	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_dpe_op_state_ctrl

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION (gen_en & gen_req_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

FSM Coverage for Module : keymgr_dpe_op_state_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	3	60.00	(Not included in score)
Transitions	8	4	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StAdv	90	Covered	T1,T4,T5
StDis	88	Not Covered
StErase	94	Not Covered
StIdle	106	Covered	T1,T2,T3
StWait	92	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
StAdv->StIdle	116	Covered	T1,T4,T5
StDis->StIdle	106	Not Covered
StErase->StIdle	106	Not Covered
StIdle->StAdv	90	Covered	T1,T4,T5
StIdle->StDis	88	Not Covered
StIdle->StErase	94	Not Covered
StIdle->StWait	92	Covered	T1,T4,T5
StWait->StIdle	127	Covered	T1,T4,T5

---

Branch Coverage for Module : keymgr_dpe_op_state_ctrl

	Line No.	Total	Covered	Percent
Branches		13	10	76.92
IF	68	2	2	100.00
CASE	85	11	8	72.73

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_op_state_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if (dis_req_i)
-3-:	89	if (adv_req_i)
-4-:	91	if (gen_req_i)
-5-:	93	if (erase_req_i)
-6-:	113	if (kmac_done_i)
-7-:	125	if (kmac_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	Covered	T1,T4,T5
StIdle	0	0	1	-	-	-	Covered	T1,T4,T5
StIdle	0	0	0	1	-	-	Not Covered
StIdle	0	0	0	0	-	-	Covered	T1,T2,T3
StErase StDis	-	-	-	-	-	-	Not Covered
StAdv	-	-	-	-	1	-	Covered	T1,T4,T5
StAdv	-	-	-	-	0	-	Covered	T1,T4,T5
StWait	-	-	-	-	-	1	Covered	T1,T4,T5
StWait	-	-	-	-	-	0	Covered	T1,T4,T5
default	-	-	-	-	-	-	Covered	T9,T10,T11

---

Assert Coverage for Module : keymgr_dpe_op_state_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	1661116	1599621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1661116	1599621	0	0
T1	59486	59398	0	0
T2	805	755	0	0
T3	1282	1212	0	0
T4	8893	8820	0	0
T5	5138	5069	0	0
T15	1278	1226	0	0
T16	1042	954	0	0
T17	1055	986	0	0
T18	1245	1165	0	0
T19	1366	1288	0	0