Unified Coverage Report :: Module :: keymgr_dpe_ctrl

Module : keymgr_dpe_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.76	89.84	77.44		46.15	79.66	85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	75.76	89.84	77.44		46.15	79.66	85.71

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.76	89.84	77.44		46.15	79.66	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.55	91.67	74.07	100.00	56.67	80.56	92.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.17	100.00	79.12	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_data_en	80.02	92.31	50.00		77.78	80.00	100.00
u_err	78.85	96.08	60.47			80.00
u_hw_sel	100.00	100.00				100.00	100.00
u_op_state	77.01	88.37	66.67		50.00	80.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
TOTAL		128	115	89.84
ALWAYS	93	4	4	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	220	3	3	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
ALWAYS	246	3	3	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	271	21	18	85.71
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
ALWAYS	387	3	3	100.00
ALWAYS	394	47	37	78.72
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
ALWAYS	559	5	5	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	622	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	656	1	1	100.00
ALWAYS	750	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
97	1	1
99	1	1
103	1	1
123	1	1
132	1	1
133	1	1
134	1	1
149	1	1
150	1	1
151	1	1
152	1	1
166	1	1
171	1	1
177	1	1
179	1	1
194	1	1
202	1	1
213	1	1
220	1	1
221	1	1
223	1	1
230	1	1
235	1	1
238	2	2
246	1	1
248	1	1
250	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
264	1	1
271	1	1
273	1	1
279	1	1
280	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
316	0	1
317	0	1
319	0	1
329	1	1
331	1	1
332	1	1
333	1	1
370	1	1
384	1	1
387	3	3
394	1	1
401	1	1
404	1	1
405	1	1
408	1	1
411	1	1
414	1	1
417	1	1
421	1	1
423	1	1
428	1	1
431	1	1
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
440	1	1
444	1	1
445	1	1
446	0	1
447	1	1
448	1	1
			MISSING_ELSE
457	1	1
461	1	1
462	1	1
463	0	1
464	1	1
465		unreachable
466		unreachable
			MISSING_ELSE
473	1	1
477	1	1
479	1	1
480	0	1
482	1	1
489	1	1
492	1	1
496	1	1
497	0	1
498	1	1
499	0	1
			MISSING_ELSE
509	1	1
512	1	1
514	1	1
516	1	1
520	0	1
521	0	1
530	0	1
532	0	1
533	0	1
			==> MISSING_ELSE
540	1	1
552	1	1
553	1	1
559	1	1
560	1	1
564	1	1
565	1	1
566	1	1
			MISSING_ELSE
617	1	1
622	1	1
625	1	1
629	1	1
636	1	1
640	1	1
643	1	1
645	1	1
651	1	1
656	1	1
750	3	3

---

Cond Coverage for Module : keymgr_dpe_ctrl

	Total	Covered	Percent
Conditions	195	151	77.44
Logical	195	151	77.44
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION ((op_i == OpDpeGenSwOut) | (op_i == OpDpeGenHwOut))
             -----------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       123
 SUB-EXPRESSION (op_i == OpDpeGenSwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       123
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       132
 EXPRESSION (op_start_i & (op_i == OpDpeAdvance) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       132
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       133
 EXPRESSION (op_start_i & (op_i == OpDpeGenHwOut) & en_i)
             -----1----   -----------2-----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       133
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       134
 EXPRESSION (op_start_i & (op_i == OpDpeDisable) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       134
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       149
 EXPRESSION (op_req & (op_i == OpDpeAdvance))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       149
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       150
 EXPRESSION (op_req & gen_key_op)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (op_req & (op_i == OpDpeErase))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       151
 SUB-EXPRESSION (op_i == OpDpeErase)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (op_req & (op_i == OpDpeDisable))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       152
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       166
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T1,T4,T5

 LINE       166
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T5

 LINE       194
 EXPRESSION (wipe_req ? SlotWipeAll : ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T11

 LINE       194
 SUB-EXPRESSION ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel))
                 --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 SUB-EXPRESSION (state_q == StCtrlDpeRandom)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 SUB-EXPRESSION ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       194
 SUB-EXPRESSION (init_o & en_i & root_key_i.valid)
                 ---1--   --2-   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       202
 EXPRESSION 
 Number  Term
      1  (op_update & op_fault_err) ? SlotWipeAll : ((op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       202
 SUB-EXPRESSION (op_update & op_fault_err)
                 ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       202
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       202
 SUB-EXPRESSION (op_update & dis_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Not Covered

 LINE       202
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       202
 SUB-EXPRESSION (op_update & (op_err | fsm_at_disabled))
                 ----1----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T7,T8

 LINE       202
 SUB-EXPRESSION (op_err | fsm_at_disabled)
                 ---1--   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

 LINE       202
 SUB-EXPRESSION ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       202
 SUB-EXPRESSION (op_update & adv_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       202
 SUB-EXPRESSION ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)
                 -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       202
 SUB-EXPRESSION (op_update & erase_req)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 EXPRESSION (random_req | fsm_at_disabled | fsm_at_invalid | wipe_req)
             -----1----   -------2-------   -------3------   ----4---

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T9,T10,T11
0	0	1	0	Covered	T9,T10,T11
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T4,T5

 LINE       230
 EXPRESSION (adv_req || gen_req)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       235
 EXPRESSION (active_key_slot_o.valid && ((!invalid_op)) && (adv_req || gen_req))
             -----------1-----------    -------2-------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T5

 LINE       235
 SUB-EXPRESSION (adv_req || gen_req)
                 ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (release_real_key ? active_key_slot_o.key[0] : ({EntropyRounds {entropy_i[0]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       238
 EXPRESSION (release_real_key ? active_key_slot_o.key[1] : ({EntropyRounds {entropy_i[1]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       260
 EXPRESSION (op_ack & gen_key_op & ((~invalid_op)))
             ---1--   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T4,T5

 LINE       261
 EXPRESSION (update_sel == SlotWipeAll)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T11

 LINE       345
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       345
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       370
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       370
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T4,T5

 LINE       428
 EXPRESSION (op_start_i & (((~en_i)) | (en_i & (op_i != OpDpeAdvance))))
             -----1----   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T6,T8

 LINE       428
 SUB-EXPRESSION (((~en_i)) | (en_i & (op_i != OpDpeAdvance)))
                 ----1----   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION (en_i & (op_i != OpDpeAdvance))
                 --1-   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       428
 SUB-EXPRESSION (op_i != OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Unreachable	T1,T4,T5

 LINE       479
 EXPRESSION (((!en_i)) | inv_state | ((~root_key_i.valid)))
             ----1----   ----2----   ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T5
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       492
 EXPRESSION (invalid_advance | invalid_erase | invalid_gen | (((~en_i)) & op_start_i))
             -------1-------   ------2------   -----3-----   ------------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T4,T5
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T5,T6
0	1	0	0	Not Covered
1	0	0	0	Covered	T6,T7,T8

 LINE       492
 SUB-EXPRESSION (((~en_i)) & op_start_i)
                 ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       496
 EXPRESSION (((!en_i)) | inv_state)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       552
 EXPRESSION (state_q == StCtrlDpeDisabled)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       553
 EXPRESSION (state_q == StCtrlDpeInvalid)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T10,T11

 LINE       564
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       625
 EXPRESSION (active_slot_boot_stage == (keymgr_dpe_pkg::DpeNumBootStages - 1))
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       636
 EXPRESSION (active_slot_policy.retain_parent ? ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid) : (slot_src_sel_i != slot_dst_sel_i))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       636
 SUB-EXPRESSION ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid)
                 -----------------1----------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Not Covered

 LINE       636
 SUB-EXPRESSION (slot_src_sel_i == slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       636
 SUB-EXPRESSION (slot_src_sel_i != slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       640
 EXPRESSION (adv_req & (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent))
             ---1---   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T7,T8

 LINE       640
 SUB-EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
                 ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T4,T5
0	0	0	1	Covered	T1,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T6,T7,T8
1	0	0	0	Not Covered

 LINE       643
 EXPRESSION (erase_req & ((~destination_slot_valid)))
             ----1----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       645
 EXPRESSION (gen_req & (((~active_key_slot_o.valid)) | ((~key_version_vld_o))))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T6

 LINE       645
 SUB-EXPRESSION (((~active_key_slot_o.valid)) | ((~key_version_vld_o)))
                 --------------1-------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       651
 EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
             ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T4,T5
0	0	0	1	Covered	T1,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T6,T7,T8
1	0	0	0	Not Covered

 LINE       658
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Not Covered

---

FSM Coverage for Module : keymgr_dpe_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	7	77.78	(Not included in score)
Transitions	13	6	46.15
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlDpeAvailable	482	Covered	T1,T4,T5
StCtrlDpeDisabled	521	Not Covered
StCtrlDpeDisabling	499	Not Covered
StCtrlDpeEntropyReseed	434	Covered	T1,T4,T5
StCtrlDpeInvalid	432	Covered	T9,T10,T11
StCtrlDpeRandom	448	Covered	T1,T4,T5
StCtrlDpeReset	94	Covered	T1,T2,T3
StCtrlDpeRootKey	466	Covered	T1,T4,T5
StCtrlDpeWipe	497	Covered	T9,T10,T11

transitions	Line No.	Covered	Tests
StCtrlDpeAvailable->StCtrlDpeDisabling	499	Not Covered
StCtrlDpeAvailable->StCtrlDpeWipe	497	Not Covered
StCtrlDpeDisabled->StCtrlDpeWipe	533	Not Covered
StCtrlDpeDisabling->StCtrlDpeDisabled	521	Not Covered
StCtrlDpeEntropyReseed->StCtrlDpeInvalid	446	Not Covered
StCtrlDpeEntropyReseed->StCtrlDpeRandom	448	Covered	T1,T4,T5
StCtrlDpeRandom->StCtrlDpeInvalid	463	Not Covered
StCtrlDpeRandom->StCtrlDpeRootKey	466	Covered	T1,T4,T5
StCtrlDpeReset->StCtrlDpeEntropyReseed	434	Covered	T1,T4,T5
StCtrlDpeReset->StCtrlDpeInvalid	432	Covered	T9,T10,T11
StCtrlDpeRootKey->StCtrlDpeAvailable	482	Covered	T1,T4,T5
StCtrlDpeRootKey->StCtrlDpeInvalid	480	Not Covered
StCtrlDpeWipe->StCtrlDpeInvalid	516	Covered	T9,T10,T11

---

Branch Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
Branches		59	47	79.66
TERNARY	194	4	4	100.00
TERNARY	202	6	3	50.00
TERNARY	370	2	2	100.00
TERNARY	636	2	2	100.00
TERNARY	238	2	2	100.00
TERNARY	238	2	2	100.00
CASE	93	4	4	100.00
IF	220	2	2	100.00
IF	246	2	2	100.00
CASE	273	6	5	83.33
IF	387	2	2	100.00
CASE	423	19	11	57.89
IF	560	4	4	100.00
IF	750	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	194	(wipe_req) ? 
-2-:	194	((state_q == StCtrlDpeRandom)) ? 
-3-:	194	(((init_o & en_i) & root_key_i.valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9,T10,T11
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	((op_update & op_fault_err)) ? 
-2-:	202	((op_update & dis_req)) ? 
-3-:	202	((op_update & (op_err | fsm_at_disabled))) ? 
-4-:	202	((op_update & adv_req)) ? 
-5-:	202	((op_update & erase_req)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Covered	T6,T7,T8
0	0	0	1	-	Covered	T1,T4,T5
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	370	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	636	(active_slot_policy.retain_parent) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	case (state_q)

Branches:

-1-	Status	Tests
StCtrlDpeReset StCtrlDpeEntropyReseed StCtrlDpeRandom StCtrlDpeRootKey	Covered	T1,T2,T3
StCtrlDpeAvailable	Covered	T1,T4,T5
StCtrlDpeWipe StCtrlDpeDisabling StCtrlDpeDisabled	Covered	T9,T10,T11
default	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	220	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	case (update_sel)

Branches:

-1-	Status	Tests
SlotDestRandomize	Covered	T1,T4,T5
SlotLoadRoot	Covered	T1,T4,T5
SlotLoadFromKmac	Covered	T1,T4,T5
SlotErase	Not Covered
SlotWipeAll SlotWipeInternalOnly	Covered	T9,T10,T11
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	387	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	case (state_q)
-2-:	431	if (inv_state)
-3-:	433	if (advance_cmd)
-4-:	445	if ((!en_i))
-5-:	447	if (prng_reseed_ack_i)
-6-:	462	if ((!en_i))
-7-:	464	if ((int'(cnt) == (EntropyRounds - 1)))
-8-:	479	if ((((!en_i) | inv_state) | (~root_key_i.valid)))
-9-:	496	if (((!en_i) | inv_state))
-10-:	498	if (disable_cmd)
-11-:	532	if ((!en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StCtrlDpeReset	1	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
StCtrlDpeReset	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StCtrlDpeReset	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDpeEntropyReseed	-	-	1	-	-	-	-	-	-	-	Not Covered
StCtrlDpeEntropyReseed	-	-	0	1	-	-	-	-	-	-	Covered	T1,T4,T5
StCtrlDpeEntropyReseed	-	-	0	0	-	-	-	-	-	-	Covered	T1,T4,T5
StCtrlDpeRandom	-	-	-	-	1	-	-	-	-	-	Not Covered
StCtrlDpeRandom	-	-	-	-	0	1	-	-	-	-	Unreachable	T1,T4,T5
StCtrlDpeRandom	-	-	-	-	0	0	-	-	-	-	Covered	T1,T4,T5
StCtrlDpeRootKey	-	-	-	-	-	-	1	-	-	-	Not Covered
StCtrlDpeRootKey	-	-	-	-	-	-	0	-	-	-	Covered	T1,T4,T5
StCtrlDpeAvailable	-	-	-	-	-	-	-	1	-	-	Not Covered
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	1	-	Not Covered
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
StCtrlDpeWipe	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
StCtrlDpeDisabling	-	-	-	-	-	-	-	-	-	-	Not Covered
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	1	Not Covered
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	0	Not Covered
StCtrlDpeInvalid	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	560	if (op_done_o)
-2-:	564	((|{error_o, fault_o})) ? 
-3-:	565	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T4,T5
1	0	-	Covered	T1,T4,T5
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	1610574	1519	0	0
DataEnDis_A	1527206	1119	0	0
DataEn_A	1527206	641848	0	0
LoadKey_A	1577748	1044757	0	0
SameErrCnt_A	105	105	0	0
SecCmCFILinear_A	1661116	0	0	200
u_state_regs_A	1661116	1599621	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610574	1519	0	0
T1	59486	16	0	0
T2	805	0	0	0
T3	1282	0	0	0
T4	8893	28	0	0
T5	5138	17	0	0
T6	0	26	0	0
T7	0	18	0	0
T8	0	18	0	0
T9	0	120	0	0
T12	0	20	0	0
T13	0	17	0	0
T14	0	16	0	0
T15	1278	0	0	0
T16	1042	0	0	0
T17	1055	0	0	0
T18	1245	0	0	0
T19	1366	0	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527206	1119	0	0
T1	59486	16	0	0
T2	805	0	0	0
T3	1282	0	0	0
T4	8893	28	0	0
T5	5138	17	0	0
T6	0	26	0	0
T7	0	18	0	0
T8	0	18	0	0
T9	0	20	0	0
T12	0	20	0	0
T13	0	17	0	0
T14	0	16	0	0
T15	1278	0	0	0
T16	1042	0	0	0
T17	1055	0	0	0
T18	1245	0	0	0
T19	1366	0	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527206	641848	0	0
T1	59486	34184	0	0
T2	805	0	0	0
T3	1282	0	0	0
T4	8893	1989	0	0
T5	5138	692	0	0
T6	0	3191	0	0
T7	0	3869	0	0
T8	0	5818	0	0
T12	0	963	0	0
T13	0	168	0	0
T14	0	5025	0	0
T15	1278	0	0	0
T16	1042	0	0	0
T17	1055	0	0	0
T18	1245	0	0	0
T19	1366	0	0	0
T20	0	922	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577748	1044757	0	0
T1	59486	58051	0	0
T2	805	0	0	0
T3	1282	0	0	0
T4	8893	3011	0	0
T5	5138	1022	0	0
T6	0	5971	0	0
T7	0	6210	0	0
T8	0	10735	0	0
T12	0	1252	0	0
T13	0	308	0	0
T14	0	8564	0	0
T15	1278	0	0	0
T16	1042	0	0	0
T17	1055	0	0	0
T18	1245	0	0	0
T19	1366	0	0	0
T20	0	1200	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1661116	0	0	200

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1661116	1599621	0	0
T1	59486	59398	0	0
T2	805	755	0	0
T3	1282	1212	0	0
T4	8893	8820	0	0
T5	5138	5069	0	0
T15	1278	1226	0	0
T16	1042	954	0	0
T17	1055	986	0	0
T18	1245	1165	0	0
T19	1366	1288	0	0