KEYMGR_DPE Simulation Results

Thursday January 25 2024 20:03:30 UTC

GitHub Revision: 6d3d71452b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2216296397

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_dpe_smoke 39.280s 3.088ms 50 50 100.00
V1 csr_hw_reset keymgr_dpe_csr_hw_reset 1.280s 113.276us 5 5 100.00
V1 csr_rw keymgr_dpe_csr_rw 1.280s 235.906us 20 20 100.00
V1 csr_bit_bash keymgr_dpe_csr_bit_bash 12.390s 1.220ms 5 5 100.00
V1 csr_aliasing keymgr_dpe_csr_aliasing 5.380s 228.623us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_dpe_csr_mem_rw_with_rand_reset 1.870s 27.405us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_dpe_csr_rw 1.280s 235.906us 20 20 100.00
keymgr_dpe_csr_aliasing 5.380s 228.623us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 intr_test keymgr_dpe_intr_test 0.940s 21.513us 50 50 100.00
V2 alert_test keymgr_dpe_alert_test 1.000s 84.020us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_dpe_tl_errors 4.800s 139.170us 20 20 100.00
V2 tl_d_illegal_access keymgr_dpe_tl_errors 4.800s 139.170us 20 20 100.00
V2 tl_d_outstanding_access keymgr_dpe_csr_hw_reset 1.280s 113.276us 5 5 100.00
keymgr_dpe_csr_rw 1.280s 235.906us 20 20 100.00
keymgr_dpe_csr_aliasing 5.380s 228.623us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.350s 91.172us 20 20 100.00
V2 tl_d_partial_access keymgr_dpe_csr_hw_reset 1.280s 113.276us 5 5 100.00
keymgr_dpe_csr_rw 1.280s 235.906us 20 20 100.00
keymgr_dpe_csr_aliasing 5.380s 228.623us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.350s 91.172us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S tl_intg_err keymgr_dpe_sec_cm 18.020s 1.426ms 5 5 100.00
keymgr_dpe_tl_intg_err 7.550s 228.396us 20 20 100.00
V2S shadow_reg_update_error keymgr_dpe_shadow_reg_errors 2.730s 274.173us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_dpe_shadow_reg_errors 2.730s 274.173us 20 20 100.00
V2S shadow_reg_storage_error keymgr_dpe_shadow_reg_errors 2.730s 274.173us 20 20 100.00
V2S shadowed_reset_glitch keymgr_dpe_shadow_reg_errors 2.730s 274.173us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_dpe_shadow_reg_errors_with_csr_rw 9.640s 349.503us 20 20 100.00
V2S prim_count_check keymgr_dpe_sec_cm 18.020s 1.426ms 5 5 100.00
V2S prim_fsm_check keymgr_dpe_sec_cm 18.020s 1.426ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset keymgr_dpe_stress_all_with_rand_reset 0.750s 4.204us 0 50 0.00
V3 TOTAL 0 50 0.00
Unmapped tests keymgr_dpe_stress_all 0.650s 0 50 0.00
TOTAL 310 410 75.61

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 4 4 4 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
73.72 97.18 89.63 57.52 61.54 93.92 98.34 17.92

Failure Buckets

Past Results