Unified Coverage Report :: Module :: keymgr_dpe

Module : keymgr_dpe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.39	100.00	80.22	53.88		97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.39	100.00	80.22	53.88		97.83	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.39	100.00	80.22	53.88		97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.01	97.70	90.62	57.52	76.92	94.94	98.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_dpe_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	79.82	89.47	72.22			77.78
u_checks	100.00	100.00					100.00
u_ctrl	89.40	96.39	82.16	100.00	76.67	88.89	92.31
u_fault_alert	100.00			100.00
u_intr_op_done	93.75	100.00	75.00			100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_kmac_if	93.59	100.00	76.06	95.24	100.00	90.24	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_max_key_ver_regwen	67.84	78.95	57.89			66.67
u_op_err_alert	100.00			100.00
u_reg	98.17	98.11	95.65	100.00		97.07	100.00
u_reseed_ctrl	98.36	100.00	91.80	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	79.42	96.30	75.47		33.33	92.00	100.00
u_slot_policy_regwen	67.84	78.95	57.89			66.67
u_sw_binding_regwen	67.84	78.95	57.89			66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
ALWAYS	446	3	3	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	480	6	6	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
ALWAYS	757	5	5	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	815	0	0
CONT_ASSIGN	821	1	1	100.00
CONT_ASSIGN	822	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
228	1	1
229	1	1
231	1	1
232	1	1
264	2	2
268	1	1
283	1	1
337	1	1
339	1	1
357	1	1
368	1	1
369	1	1
370	1	1
417	1	1
418	1	1
419	1	1
441	1	1
446	1	1
447	1	1
448	1	1
457	1	1
459	1	1
470	1	1
472	1	1
480	1	1
481	1	1
483	1	1
489	1	1
493	1	1
494	1	1
502	1	1
503	1	1
506	1	1
508	1	1
513	1	1
544	1	1
545	1	1
546	1	1
547	1	1
548	1	1
549	1	1
550	1	1
551	1	1
552	1	1
557	1	1
558	1	1
559	1	1
560	1	1
563	1	1
567	1	1
568	1	1
570	1	1
581	1	1
586	1	1
587	1	1
706	1	1
707	1	1
708	1	1
710	1	1
711	1	1
712	1	1
713	1	1
714	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
747	1	1
749	1	1
752	1	1
753	1	1
757	1	1
758	1	1
759	1	1
761	1	1
762	1	1
767	1	1
784	1	1
815		unreachable
821	1	1
822	1	1

---

Cond Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Conditions	182	146	80.22
Logical	182	146	80.22
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T4,T5,T6

 LINE       208
 EXPRESSION (seed_en & ((~reg2hw.start.q)))
             ---1---   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       273
 EXPRESSION (otp_key_i.creator_root_key_share0_valid & otp_key_i.creator_root_key_share1_valid)
             -------------------1-------------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       347
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       368
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       369
 EXPRESSION (reg2hw.slot_policy_regwen.qe & ((~reg2hw.slot_policy_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       370
 EXPRESSION (reg2hw.max_key_ver_regwen.qe & ((~reg2hw.max_key_ver_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       417
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (slot_policy_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       419
 EXPRESSION (max_key_ver_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       489
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       503
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       508
 EXPRESSION (active_key_slot.valid ? ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}) : ({GenLfsrCopies {lfsr[31:0]}}))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       557
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       557
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       558
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       558
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       559
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       559
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       560
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION (adv_en & (active_key_slot.boot_stage == OwnerInt))
             ---1--   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       563
 SUB-EXPRESSION (active_key_slot.boot_stage == OwnerInt)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       568
 EXPRESSION (adv_en | gen_en)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       581
 EXPRESSION (((~key_vld)) | invalid_advance | ((~adv_dvalid[active_key_slot.boot_stage])))
             ------1-----   -------2-------   ---------------------3---------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T4,T5,T6
1	0	0	Not Covered

 LINE       586
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       587
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       749
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       753
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       753
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       767
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       784
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Totals	69	51	73.91
Total Bits	10582	5702	53.88
Total Bits 0->1	5291	2852	53.90
Total Bits 1->0	5291	2850	53.87

Ports	69	51	73.91
Port Bits	10582	5702	53.88
Port Bits 0->1	5291	2852	53.90
Port Bits 1->0	5291	2850	53.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T17,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T12,T15,T16	Yes	T12,T15,T16	INPUT
tl_i.a_user.rsvd[9:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T4,T5,T6	INPUT
tl_i.a_address[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T2,T4,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][11:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][12]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][23:13]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][24]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][34:25]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][35]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][37:36]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][38]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
aes_key_o.key[0][42:39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][43]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][44]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][68:45]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][69]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][84:70]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][85]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][86]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][94:87]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][95]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][115:96]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][116]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][121:117]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][122]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][132:123]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][133]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][134]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][159:135]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][160]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][163:161]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][165]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][166]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][174:167]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][185:176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][186]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][189:187]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][190]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][194:191]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][219:196]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][220]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][228:221]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][229]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][230]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][231]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][232]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][242:233]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][243]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][246:244]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][247]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[0][255:248]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][6:3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][7]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][9:8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][10]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][12:11]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][13]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[1][19:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][20]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
aes_key_o.key[1][29:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][30]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][31]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][35:32]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][36]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][47:37]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][48]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
aes_key_o.key[1][66:49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][67]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][70:68]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][71]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][74:72]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][91:76]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][92]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][102:93]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][104:103]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][113:105]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][114]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][129:115]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][130]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][144:131]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][145]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][162:146]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][163]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][172:164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][173]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
aes_key_o.key[1][174]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][180:175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][181]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][182]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
aes_key_o.key[1][201:183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][202]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][206:203]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][207]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][208]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][215:209]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][216]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][224:217]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][225]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][249:226]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][250]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][252]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][254:253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.valid	No	No		Yes	T4,T5,T6	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_key_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][5:4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][6]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][7]	Yes	Yes	T5,T10,T12	Yes	T5,T10,T12	OUTPUT
otbn_key_o.key[0][8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][11:9]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][13:12]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][16:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][17]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][20:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][22]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][25:23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][26]	Yes	Yes	T6,T10,T11	Yes	T6,T10,T11	OUTPUT
otbn_key_o.key[0][31:27]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][32]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][36:33]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][37]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][38]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][40]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][41]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][43:42]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][45:44]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][46]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][47]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][48]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][50:49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][51]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][52]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][55:53]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][56]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][58:57]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][59]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][61]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][64:62]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][65]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][66]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][67]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][68]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][69]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][72:70]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][73]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][74]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][79:75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][81:80]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][83:82]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][84]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][88:85]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][89]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][94:90]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][95]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][96]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][97]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][99:98]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][102:100]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][103]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][104]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][108:105]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][109]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][110]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][111]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][112]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][113]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][117:114]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][118]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][119]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][120]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][124:121]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][125]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][128:126]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][129]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][131:130]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][134:133]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][135]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][136]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][137]	Yes	Yes	T6,T10,T11	Yes	T6,T10,T11	OUTPUT
otbn_key_o.key[0][141:138]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][142]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][143]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][145:144]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][149:146]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][150]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][152:151]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][153]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][155:154]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][156]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][158:157]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][159]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][160]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][162:161]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][163]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][165:164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][166]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][167]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][169:168]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][170]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][172:171]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][174:173]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][177]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][179:178]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][180]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][181]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][182]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][184:183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][185]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][197:186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][199:198]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][200]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][201]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][202]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][203]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][205:204]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][206]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][208:207]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][209]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][211]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][212]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][215:213]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][218:216]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][219]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][220]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][222:221]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][223]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][224]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][230:225]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][233:232]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][236:234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][239:237]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][241]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][243]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][246:244]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][247]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][250:248]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][252]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][257:254]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][258]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][260:259]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][261]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][264:262]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][265]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][266]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][269:267]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][270]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][271]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][279:272]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][280]	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	OUTPUT
otbn_key_o.key[0][281]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][283:282]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][284]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][286:285]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][287]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][288]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][291:289]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][292]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][293]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][295:294]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][296]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][297]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][298]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][299]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][300]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][301]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][302]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][303]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][304]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][305]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][306]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][308:307]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][309]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][310]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][313:311]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][314]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][315]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][316]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][321:317]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][322]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][323]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][324]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][326:325]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][327]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][331:328]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][332]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][334:333]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][338:335]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][339]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][340]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][342:341]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][343]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][345:344]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][346]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][347]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][348]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][350:349]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][351]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][352]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][353]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][354]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][356:355]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][357]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][358]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][359]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][360]	Yes	Yes	T6,T10,T11	Yes	T6,T10,T11	OUTPUT
otbn_key_o.key[0][365:361]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][366]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][367]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][368]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][369]	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	OUTPUT
otbn_key_o.key[0][370]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][372:371]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][373]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][374]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][375]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][379:376]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][380]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][381]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][383:382]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][2]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][6:5]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][7]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][9:8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][10]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][12:11]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][13]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][15:14]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][19:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][20]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][22]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][32:24]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][33]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][34]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][38:35]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][40]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][41]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][43:42]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][44]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][45]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][48:46]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][50:49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][51]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][56:52]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][57]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][58]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][59]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][61:60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][62]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][63]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][64]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][65]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][67:66]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][68]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][69]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][70]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][71]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][72]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][73]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][74]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][77:76]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][78]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][79]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][80]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][82:81]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][88:83]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][89]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][90]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][91]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][92]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][93]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][94]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][95]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][96]	Yes	Yes	T4,T10,T11	Yes	T4,T10,T11	OUTPUT
otbn_key_o.key[1][98:97]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][99]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][100]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][107:101]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][108]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][112:109]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][113]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][114]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][119:115]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][120]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][121]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][127:122]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][128]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][129]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][131:130]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][134:133]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][135]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][137:136]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][138]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][139]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][140]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][141]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][142]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][143]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][144]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][145]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][146]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][151:147]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][152]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][153]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][156:154]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][157]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][159:158]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][160]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][161]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][164:162]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][165]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][166]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][167]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][169:168]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][171:170]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][173:172]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][174]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][177]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][180:178]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][181]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][182]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][185:183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][188:186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][189]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][190]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][191]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][192]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][193]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][194]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][196]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][197]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][198]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][199]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][200]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][201]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][203:202]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][204]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][206:205]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][207]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][208]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][209]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][212:210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][213]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][214]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][215]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][216]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][217]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][218]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][220:219]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][225:221]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][226]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][227]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][229:228]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][230]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][232:231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][233]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][237:234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][238]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][239]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][241]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][243]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][244]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][246:245]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][247]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][248]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][249]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][250]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][252]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][255:254]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][256]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][257]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][258]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][260:259]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][264:261]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][266:265]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][268:267]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][269]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][275:270]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][276]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][277]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][278]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][279]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][280]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][281]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][282]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][283]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][290:284]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][291]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][299:292]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][300]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][301]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][304:302]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][305]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][309:306]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][310]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][315:311]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][316]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][317]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][318]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][319]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][320]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][321]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][323:322]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][324]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][326:325]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][327]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][328]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][329]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][333:330]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][334]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][335]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][336]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][337]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][338]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][344:339]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][345]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][355:346]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][356]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][357]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][358]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][359]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][360]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][361]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][368:362]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][369]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][373:370]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][374]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][375]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][376]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][377]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][378]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][379]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][380]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][383:381]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.valid	No	No		Yes	T4,T5,T6	OUTPUT
kmac_data_o.last	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.ready	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T1,T5,T6	INPUT
lc_keymgr_div_i[127:0]	No	No		No		INPUT
otp_key_i.owner_seed_valid	No	No		No		INPUT
otp_key_i.owner_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_seed_valid	No	No		No		INPUT
otp_key_i.creator_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	No	No		No		INPUT
otp_device_id_i[255:0]	No	No		No		INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T5,T6,T10	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T4,T5,T6	Yes	T5,T6,T10	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_digest_i[0].valid	No	No		No		INPUT
rom_digest_i[0].data[255:0]	No	No		No		INPUT
rom_digest_i[1].valid	No	No		No		INPUT
rom_digest_i[1].data[255:0]	No	No		No		INPUT
intr_op_done_o	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	503	4	4	100.00
TERNARY	508	2	2	100.00
TERNARY	749	3	2	66.67
TERNARY	753	3	3	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
IF	757	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	503	((dest_sel == Aes)) ? 
-2-:	503	((dest_sel == Kmac)) ? 
-3-:	503	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	508	(active_key_slot.valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	749	(fault_errs) ? 
-2-:	749	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T8,T9
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	753	(op_errs) ? 
-2-:	753	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	757	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	104	104	0	0
AesKeyKnownO_A	4830560	4768897	0	0
AlertKnownO_A	4830560	4768897	0	0
ErrCntMatch_A	104	104	0	0
FaultCntMatch_A	104	104	0	0
FpvSecCmCtrlCntAlertCheck_A	4830560	80	0	0
FpvSecCmCtrlDataFsmCheck_A	4830560	80	0	0
FpvSecCmCtrlMainFsmCheck_A	4830560	80	0	0
FpvSecCmCtrlOpFsmCheck_A	4830560	80	0	0
FpvSecCmKmacIfCntAlertCheck_A	4830560	80	0	0
FpvSecCmKmacIfFsmCheck_A	4830560	80	0	0
FpvSecCmRegWeOnehotCheck_A	4830560	80	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	4830560	80	0	0
FpvSecCmSideloadCtrlFsmCheck_A	4830560	80	0	0
GenDataWidth_A	104	104	0	0
IntrKnownO_A	4830560	4768897	0	0
KeyWidthEqualityCheck_A	104	104	0	0
KmacDataKnownO_A	4788702	4727039	0	0
KmacKeyKnownO_A	4830560	4768897	0	0
KmacMaskCheck_A	104	104	0	0
LfsrWidth_A	104	104	0	0
OtbnKeyKnownO_A	4830560	4768897	0	0
OutputKeyDiff_A	104	104	0	0
TlAReadyKnownO_A	4830560	4768897	0	0
TlDValidKnownO_A	4830560	4768897	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	80	0	0
T7	63310	10	0	0
T8	34643	10	0	0
T9	0	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	65054	0	0	0
T25	829	0	0	0
T26	51892	0	0	0
T27	897	0	0	0
T28	68753	0	0	0
T29	1016	0	0	0
T30	1084	0	0	0
T31	1209	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

KeyWidthEqualityCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4788702	4727039	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4830560	4768897	0	0
T1	719	665	0	0
T2	976	910	0	0
T3	1256	1178	0	0
T4	22447	22365	0	0
T5	40993	40926	0	0
T6	59421	59361	0	0
T10	22249	22163	0	0
T11	63830	63780	0	0
T17	1269	1199	0	0
T18	1545	1478	0	0