Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	6255267	7701	0	0
intr_enable_rd_A	6255267	3205	0	0
key_version_rd_A	6255267	2783	0	0
reseed_interval_regwen_rd_A	6255267	1072	0	0
salt_0_rd_A	6255267	3028	0	0
salt_1_rd_A	6255267	2925	0	0
salt_2_rd_A	6255267	2951	0	0
salt_3_rd_A	6255267	2911	0	0
salt_4_rd_A	6255267	2803	0	0
salt_5_rd_A	6255267	2818	0	0
salt_6_rd_A	6255267	3029	0	0
salt_7_rd_A	6255267	3013	0	0
sideload_clear_rd_A	6255267	2969	0	0
slot_policy_rd_A	6255267	4211	0	0
sw_binding_0_rd_A	6255267	2854	0	0
sw_binding_1_rd_A	6255267	2807	0	0
sw_binding_2_rd_A	6255267	2832	0	0
sw_binding_3_rd_A	6255267	2817	0	0
sw_binding_4_rd_A	6255267	3012	0	0
sw_binding_5_rd_A	6255267	2931	0	0
sw_binding_6_rd_A	6255267	2789	0	0
sw_binding_7_rd_A	6255267	2980	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	7701	0	0
T19	3997	101	0	0
T20	4384	498	0	0
T21	1999	11	0	0
T32	12161	467	0	0
T33	0	400	0	0
T34	12115	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T91	1387	47	0	0
T92	2638	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	3205	0	0
T32	0	8	0	0
T33	0	7	0	0
T34	12115	22	0	0
T37	14861	63	0	0
T46	1210	10	0	0
T64	14750	32	0	0
T68	9134	27	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	14	0	0
T86	1688	3	0	0
T92	2638	7	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2783	0	0
T32	12161	25	0	0
T34	12115	18	0	0
T36	0	92	0	0
T37	14861	56	0	0
T43	0	5	0	0
T47	0	29	0	0
T64	14750	46	0	0
T68	9134	31	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	9	0	0
T92	2638	10	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	1072	0	0
T32	12161	28	0	0
T34	12115	0	0	0
T35	16292	0	0	0
T37	14861	1	0	0
T57	0	9	0	0
T64	14750	38	0	0
T68	9134	22	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T92	2638	7	0	0
T93	0	1	0	0
T94	0	11	0	0
T95	0	15	0	0
T96	0	55	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	3028	0	0
T32	12161	22	0	0
T33	0	10	0	0
T34	12115	8	0	0
T36	0	73	0	0
T37	14861	41	0	0
T47	0	48	0	0
T64	14750	42	0	0
T68	9134	23	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	8	0	0
T92	2638	9	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2925	0	0
T32	12161	17	0	0
T33	0	5	0	0
T34	12115	16	0	0
T35	16292	0	0	0
T36	0	78	0	0
T37	14861	49	0	0
T43	0	5	0	0
T47	0	59	0	0
T64	14750	34	0	0
T68	9134	13	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	2	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2951	0	0
T32	12161	18	0	0
T34	12115	18	0	0
T35	16292	0	0	0
T36	0	85	0	0
T37	14861	48	0	0
T43	0	2	0	0
T47	0	35	0	0
T64	14750	15	0	0
T68	9134	15	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	2	0	0
T93	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2911	0	0
T32	12161	3	0	0
T33	0	17	0	0
T34	12115	32	0	0
T36	0	100	0	0
T37	14861	64	0	0
T43	0	2	0	0
T64	14750	50	0	0
T68	9134	11	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	9	0	0
T92	2638	12	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2803	0	0
T32	12161	0	0	0
T34	12115	29	0	0
T36	0	83	0	0
T37	14861	46	0	0
T43	0	5	0	0
T47	0	49	0	0
T64	14750	50	0	0
T68	9134	17	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	1	0	0
T92	2638	6	0	0
T93	0	5	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2818	0	0
T32	12161	18	0	0
T33	0	10	0	0
T34	12115	13	0	0
T36	0	92	0	0
T37	14861	49	0	0
T43	0	11	0	0
T64	14750	43	0	0
T68	9134	7	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	2	0	0
T92	2638	3	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	3029	0	0
T32	12161	14	0	0
T34	12115	24	0	0
T35	16292	0	0	0
T36	0	84	0	0
T37	14861	60	0	0
T43	0	9	0	0
T47	0	19	0	0
T64	14750	59	0	0
T68	9134	21	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	9	0	0
T93	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	3013	0	0
T32	12161	16	0	0
T33	0	8	0	0
T34	12115	24	0	0
T35	16292	0	0	0
T36	0	71	0	0
T37	14861	54	0	0
T47	0	39	0	0
T64	14750	50	0	0
T68	9134	8	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	1	0	0
T93	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2969	0	0
T32	12161	12	0	0
T33	0	7	0	0
T34	12115	15	0	0
T36	0	85	0	0
T37	14861	35	0	0
T47	0	44	0	0
T64	14750	41	0	0
T68	9134	24	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	6	0	0
T92	2638	7	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	4211	0	0
T32	12161	8	0	0
T33	0	8	0	0
T34	12115	49	0	0
T35	16292	0	0	0
T36	0	197	0	0
T37	14861	88	0	0
T43	0	6	0	0
T47	0	60	0	0
T64	14750	40	0	0
T68	9134	21	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	20	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2854	0	0
T32	12161	18	0	0
T33	0	3	0	0
T34	12115	15	0	0
T36	0	76	0	0
T37	14861	51	0	0
T47	0	48	0	0
T64	14750	25	0	0
T68	9134	6	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	9	0	0
T92	2638	10	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2807	0	0
T32	12161	4	0	0
T34	12115	19	0	0
T36	0	84	0	0
T37	14861	25	0	0
T47	0	48	0	0
T64	14750	25	0	0
T68	9134	23	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	5	0	0
T92	2638	6	0	0
T93	0	1	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2832	0	0
T32	12161	6	0	0
T33	0	2	0	0
T34	12115	10	0	0
T36	0	91	0	0
T37	14861	38	0	0
T43	0	7	0	0
T64	14750	46	0	0
T68	9134	24	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	1	0	0
T92	2638	4	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2817	0	0
T32	12161	0	0	0
T34	12115	17	0	0
T36	0	88	0	0
T37	14861	42	0	0
T47	0	45	0	0
T64	14750	33	0	0
T68	9134	29	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	2	0	0
T92	2638	7	0	0
T93	0	9	0	0
T94	0	4	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	3012	0	0
T32	12161	17	0	0
T33	0	3	0	0
T34	12115	6	0	0
T36	0	79	0	0
T37	14861	38	0	0
T43	0	11	0	0
T64	14750	42	0	0
T68	9134	19	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	4	0	0
T92	2638	5	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2931	0	0
T32	12161	10	0	0
T33	0	10	0	0
T34	12115	32	0	0
T36	0	80	0	0
T37	14861	76	0	0
T43	0	8	0	0
T64	14750	36	0	0
T68	9134	15	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	5	0	0
T92	2638	5	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2789	0	0
T32	12161	0	0	0
T34	12115	37	0	0
T36	0	91	0	0
T37	14861	45	0	0
T47	0	44	0	0
T64	14750	46	0	0
T68	9134	2	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	2	0	0
T92	2638	2	0	0
T93	0	10	0	0
T94	0	13	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6255267	2980	0	0
T32	12161	8	0	0
T34	12115	33	0	0
T36	0	68	0	0
T37	14861	53	0	0
T43	0	2	0	0
T47	0	30	0	0
T64	14750	42	0	0
T68	9134	23	0	0
T69	10406	0	0	0
T70	17161	0	0	0
T71	833	0	0	0
T86	1688	5	0	0
T92	2638	4	0	0