Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1163047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238435

1

T1

1

T2

6

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1263123	1			T1	1		T2	1		T3	1
values[0x0]	68827	1			T1	3		T2	13		T3	12
values[0x1]	69532	1			T1	2		T2	8		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	790177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

611305

1

T1

2

T2

7

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4554	1			T4	344		T5	50		T10	25
valid_sources[0x01]	4407	1			T1	1		T4	282		T5	33
valid_sources[0x02]	4446	1			T2	2		T4	331		T5	42
valid_sources[0x03]	4759	1			T23	2		T4	372		T5	35
valid_sources[0x04]	4514	1			T4	349		T5	25		T10	21
valid_sources[0x05]	31714	1			T24	1		T4	268		T5	32
valid_sources[0x06]	4359	1			T4	375		T5	30		T10	25
valid_sources[0x07]	4603	1			T4	305		T5	35		T10	29
valid_sources[0x08]	4467	1			T4	337		T5	44		T10	21
valid_sources[0x09]	4422	1			T2	1		T4	355		T5	45
valid_sources[0x0a]	4656	1			T4	267		T5	33		T10	18
valid_sources[0x0b]	4437	1			T4	297		T5	37		T10	26
valid_sources[0x0c]	4631	1			T4	288		T5	25		T10	23
valid_sources[0x0d]	4142	1			T4	284		T5	34		T10	24
valid_sources[0x0e]	4669	1			T4	328		T5	23		T10	21
valid_sources[0x0f]	4621	1			T4	325		T5	26		T10	20
valid_sources[0x10]	4351	1			T2	1		T4	286		T5	26
valid_sources[0x11]	4493	1			T4	379		T5	37		T10	15
valid_sources[0x12]	5195	1			T3	3		T26	3		T4	313
valid_sources[0x13]	4391	1			T4	336		T5	25		T10	23
valid_sources[0x14]	4357	1			T4	335		T5	32		T10	15
valid_sources[0x15]	4333	1			T4	303		T5	30		T10	18
valid_sources[0x16]	4454	1			T4	335		T5	30		T10	12
valid_sources[0x17]	4631	1			T1	1		T4	361		T5	40
valid_sources[0x18]	4537	1			T4	338		T5	35		T10	24
valid_sources[0x19]	4074	1			T4	325		T5	41		T10	21
valid_sources[0x1a]	4379	1			T4	326		T5	26		T10	36
valid_sources[0x1b]	4459	1			T4	311		T5	28		T10	19
valid_sources[0x1c]	4528	1			T4	287		T5	33		T10	26
valid_sources[0x1d]	4444	1			T1	1		T4	351		T5	24
valid_sources[0x1e]	4807	1			T4	325		T5	26		T10	16
valid_sources[0x1f]	10515	1			T4	333		T5	34		T10	20
valid_sources[0x20]	4523	1			T4	336		T5	41		T10	18
valid_sources[0x21]	4052	1			T4	315		T5	32		T10	24
valid_sources[0x22]	4490	1			T20	8		T4	350		T5	38
valid_sources[0x23]	4326	1			T4	300		T5	34		T17	1
valid_sources[0x24]	4342	1			T4	262		T5	23		T10	21
valid_sources[0x25]	4264	1			T4	310		T5	34		T10	23
valid_sources[0x26]	4474	1			T4	339		T5	35		T10	25
valid_sources[0x27]	4252	1			T4	325		T5	28		T10	20
valid_sources[0x28]	4597	1			T2	1		T22	1		T4	322
valid_sources[0x29]	4844	1			T4	333		T5	35		T10	23
valid_sources[0x2a]	4265	1			T2	1		T4	336		T5	39
valid_sources[0x2b]	4632	1			T4	339		T5	37		T10	25
valid_sources[0x2c]	4594	1			T4	283		T5	34		T10	26
valid_sources[0x2d]	4424	1			T4	303		T5	39		T10	29
valid_sources[0x2e]	4340	1			T21	5		T4	313		T5	36
valid_sources[0x2f]	4535	1			T4	360		T5	28		T10	20
valid_sources[0x30]	4898	1			T4	292		T5	32		T10	22
valid_sources[0x31]	4033	1			T23	1		T4	325		T5	30
valid_sources[0x32]	4585	1			T4	341		T5	31		T10	29
valid_sources[0x33]	4705	1			T20	6		T22	1		T24	1
valid_sources[0x34]	4557	1			T4	333		T5	28		T10	30
valid_sources[0x35]	4590	1			T4	348		T5	34		T10	28
valid_sources[0x36]	4398	1			T4	344		T5	31		T10	18
valid_sources[0x37]	4091	1			T4	303		T5	37		T10	32
valid_sources[0x38]	79923	1			T4	380		T5	38		T10	27
valid_sources[0x39]	4365	1			T4	359		T5	28		T10	29
valid_sources[0x3a]	4497	1			T4	334		T5	23		T17	1
valid_sources[0x3b]	4730	1			T3	2		T22	1		T4	318
valid_sources[0x3c]	6673	1			T4	330		T5	25		T10	23
valid_sources[0x3d]	35506	1			T4	296		T5	27		T10	18
valid_sources[0x3e]	4539	1			T4	356		T5	27		T10	26
valid_sources[0x3f]	5457	1			T2	1		T4	286		T5	31
valid_sources[0x40]	4435	1			T20	1		T4	317		T5	36
valid_sources[0x41]	4396	1			T4	299		T5	41		T10	27
valid_sources[0x42]	5965	1			T4	306		T5	32		T10	28
valid_sources[0x43]	4726	1			T23	1		T4	288		T5	31
valid_sources[0x44]	4645	1			T4	321		T5	27		T17	1
valid_sources[0x45]	4699	1			T4	354		T5	39		T10	21
valid_sources[0x46]	4602	1			T2	2		T4	254		T5	34
valid_sources[0x47]	4689	1			T4	284		T5	29		T10	26
valid_sources[0x48]	4623	1			T4	334		T5	32		T10	21
valid_sources[0x49]	4263	1			T4	319		T5	42		T10	18
valid_sources[0x4a]	4176	1			T4	288		T5	32		T18	2
valid_sources[0x4b]	9052	1			T23	1		T4	338		T5	34
valid_sources[0x4c]	4556	1			T4	280		T5	34		T10	25
valid_sources[0x4d]	4782	1			T23	1		T4	322		T5	41
valid_sources[0x4e]	4541	1			T4	297		T5	43		T10	23
valid_sources[0x4f]	4999	1			T4	340		T5	34		T10	12
valid_sources[0x50]	4887	1			T3	1		T4	296		T5	36
valid_sources[0x51]	4416	1			T4	311		T5	40		T10	18
valid_sources[0x52]	4608	1			T4	275		T5	27		T10	18
valid_sources[0x53]	4448	1			T22	2		T4	315		T5	26
valid_sources[0x54]	4092	1			T4	318		T5	37		T10	23
valid_sources[0x55]	4441	1			T4	267		T5	33		T10	27
valid_sources[0x56]	4650	1			T4	307		T5	25		T10	25
valid_sources[0x57]	4607	1			T2	1		T25	40		T4	279
valid_sources[0x58]	4630	1			T4	324		T5	32		T10	17
valid_sources[0x59]	4598	1			T4	326		T5	29		T10	30
valid_sources[0x5a]	4293	1			T4	318		T5	37		T10	29
valid_sources[0x5b]	4644	1			T4	299		T5	44		T10	12
valid_sources[0x5c]	4423	1			T4	373		T5	29		T10	37
valid_sources[0x5d]	4346	1			T2	1		T4	352		T5	26
valid_sources[0x5e]	4832	1			T4	305		T5	33		T10	28
valid_sources[0x5f]	4364	1			T4	316		T5	35		T10	27
valid_sources[0x60]	4362	1			T4	319		T5	48		T10	23
valid_sources[0x61]	4661	1			T4	281		T5	38		T10	32
valid_sources[0x62]	4534	1			T3	1		T4	303		T5	36
valid_sources[0x63]	4804	1			T4	355		T5	35		T10	20
valid_sources[0x64]	4393	1			T2	1		T4	374		T5	30
valid_sources[0x65]	4263	1			T4	293		T5	25		T10	30
valid_sources[0x66]	4419	1			T4	366		T5	29		T10	38
valid_sources[0x67]	4719	1			T2	2		T4	306		T5	40
valid_sources[0x68]	4440	1			T4	335		T5	44		T10	20
valid_sources[0x69]	5564	1			T4	267		T5	28		T10	17
valid_sources[0x6a]	4615	1			T4	274		T5	33		T10	20
valid_sources[0x6b]	4877	1			T4	311		T5	26		T10	27
valid_sources[0x6c]	4681	1			T4	315		T5	29		T17	1
valid_sources[0x6d]	4635	1			T4	322		T5	34		T10	23
valid_sources[0x6e]	4419	1			T4	346		T5	41		T10	26
valid_sources[0x6f]	4888	1			T4	321		T5	31		T10	14
valid_sources[0x70]	4195	1			T4	286		T5	27		T10	28
valid_sources[0x71]	4633	1			T4	303		T5	31		T10	27
valid_sources[0x72]	4377	1			T4	302		T5	20		T10	11
valid_sources[0x73]	4228	1			T3	2		T22	1		T23	1
valid_sources[0x74]	8020	1			T4	278		T5	37		T10	25
valid_sources[0x75]	4695	1			T2	1		T4	300		T5	47
valid_sources[0x76]	4346	1			T3	1		T4	357		T5	34
valid_sources[0x77]	5003	1			T4	356		T5	39		T10	22
valid_sources[0x78]	4313	1			T4	336		T5	29		T10	22
valid_sources[0x79]	4147	1			T4	271		T5	30		T10	25
valid_sources[0x7a]	4552	1			T4	352		T5	24		T10	26
valid_sources[0x7b]	4442	1			T4	324		T5	29		T10	28
valid_sources[0x7c]	4159	1			T4	302		T5	30		T10	27
valid_sources[0x7d]	4219	1			T4	321		T5	33		T17	1
valid_sources[0x7e]	4867	1			T4	310		T5	30		T10	27
valid_sources[0x7f]	4450	1			T4	291		T5	30		T10	17
valid_sources[0x80]	4550	1			T4	346		T5	31		T10	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132736

1

T1

1

T3

1

T20

1

values[0x0]

all_enables

biggest_size

56467

1

T2

4

T3

4

T20

7

values[0x1]

all_enables

biggest_size

49232

1

T2

2

T3

2

T20

3