| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| cip_base_pkg.dut_and_edn_rsts | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 4 | 0 | 4 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| resets_trans | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 4 | 0 | 4 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| rst1_start_last_end_first | 205 | 1 | T7 | 53 | T30 | 36 | T31 | 22 | ||||
| rst1_start_first_end_last | 185 | 1 | T7 | 1 | T8 | 12 | T9 | 9 | ||||
| rst1_start_last_end_last | 562 | 1 | T8 | 168 | T9 | 81 | T30 | 65 | ||||
| rst1_start_first_end_first | 516 | 1 | T7 | 126 | T30 | 38 | T31 | 158 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |