Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10723435	8074	0	0
intr_enable_rd_A	10723435	2834	0	0
key_version_rd_A	10723435	2760	0	0
reseed_interval_regwen_rd_A	10723435	982	0	0
salt_0_rd_A	10723435	2618	0	0
salt_1_rd_A	10723435	2589	0	0
salt_2_rd_A	10723435	2651	0	0
salt_3_rd_A	10723435	2740	0	0
salt_4_rd_A	10723435	2589	0	0
salt_5_rd_A	10723435	2748	0	0
salt_6_rd_A	10723435	2605	0	0
salt_7_rd_A	10723435	2650	0	0
sideload_clear_rd_A	10723435	2553	0	0
slot_policy_rd_A	10723435	3407	0	0
sw_binding_0_rd_A	10723435	2574	0	0
sw_binding_1_rd_A	10723435	2523	0	0
sw_binding_2_rd_A	10723435	2520	0	0
sw_binding_3_rd_A	10723435	2762	0	0
sw_binding_4_rd_A	10723435	2683	0	0
sw_binding_5_rd_A	10723435	2704	0	0
sw_binding_6_rd_A	10723435	2523	0	0
sw_binding_7_rd_A	10723435	2785	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	8074	0	0
T27	2197	228	0	0
T28	5303	366	0	0
T29	2610	11	0	0
T41	11545	537	0	0
T42	10435	1	0	0
T43	0	4	0	0
T44	0	5	0	0
T49	0	100	0	0
T50	0	5	0	0
T77	4858	204	0	0
T79	5014	0	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2834	0	0
T29	2610	13	0	0
T42	10435	18	0	0
T45	1248	6	0	0
T46	4892	25	0	0
T73	10238	0	0	0
T77	0	5	0	0
T81	0	9	0	0
T104	1301	13	0	0
T105	1220	14	0	0
T106	1608	17	0	0
T107	0	25	0	0
T108	1070	0	0	0
T109	858	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2760	0	0
T29	2610	11	0	0
T42	10435	41	0	0
T43	0	68	0	0
T44	0	87	0	0
T45	1248	6	0	0
T46	4892	46	0	0
T76	0	42	0	0
T77	4858	5	0	0
T79	5014	20	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	70	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	982	0	0
T29	2610	16	0	0
T42	10435	4	0	0
T43	22890	0	0	0
T46	4892	10	0	0
T76	0	42	0	0
T77	4858	5	0	0
T79	5014	9	0	0
T80	0	14	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	13	0	0
T110	0	26	0	0
T111	0	33	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2618	0	0
T29	2610	17	0	0
T42	10435	7	0	0
T43	22890	58	0	0
T44	21538	64	0	0
T45	1248	2	0	0
T46	4892	19	0	0
T76	0	41	0	0
T78	6845	0	0	0
T79	5014	26	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	65	0	0
T112	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2589	0	0
T29	2610	10	0	0
T42	10435	22	0	0
T43	22890	46	0	0
T44	21538	69	0	0
T46	4892	12	0	0
T76	10330	25	0	0
T78	6845	0	0	0
T79	5014	20	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	102	0	0
T110	0	71	0	0
T112	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2651	0	0
T29	2610	16	0	0
T42	10435	25	0	0
T43	22890	54	0	0
T44	0	93	0	0
T45	1248	3	0	0
T76	0	48	0	0
T77	4858	6	0	0
T79	5014	16	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	99	0	0
T112	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2740	0	0
T29	2610	18	0	0
T42	10435	21	0	0
T43	22890	38	0	0
T44	21538	104	0	0
T45	1248	8	0	0
T46	4892	30	0	0
T76	0	40	0	0
T78	6845	0	0	0
T79	5014	11	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	65	0	0
T112	0	4	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2589	0	0
T29	2610	12	0	0
T42	10435	20	0	0
T43	22890	50	0	0
T44	21538	90	0	0
T45	1248	8	0	0
T46	4892	28	0	0
T76	0	23	0	0
T78	6845	0	0	0
T79	5014	27	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	62	0	0
T112	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2748	0	0
T29	2610	16	0	0
T42	10435	24	0	0
T43	0	41	0	0
T44	0	87	0	0
T45	1248	8	0	0
T46	4892	17	0	0
T76	0	46	0	0
T77	4858	3	0	0
T79	5014	11	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	73	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2605	0	0
T29	2610	15	0	0
T42	10435	40	0	0
T43	22890	39	0	0
T44	21538	84	0	0
T45	1248	8	0	0
T46	4892	8	0	0
T76	0	45	0	0
T78	6845	0	0	0
T79	5014	22	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	82	0	0
T112	0	8	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2650	0	0
T29	2610	13	0	0
T42	10435	16	0	0
T43	0	47	0	0
T44	0	79	0	0
T45	1248	6	0	0
T46	4892	31	0	0
T76	0	32	0	0
T77	4858	9	0	0
T79	5014	20	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	82	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2553	0	0
T29	2610	18	0	0
T42	10435	22	0	0
T43	22890	64	0	0
T44	21538	92	0	0
T45	1248	2	0	0
T46	4892	3	0	0
T76	0	32	0	0
T78	6845	0	0	0
T79	5014	15	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	57	0	0
T112	0	3	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	3407	0	0
T29	2610	11	0	0
T42	10435	19	0	0
T43	0	109	0	0
T44	0	188	0	0
T45	1248	17	0	0
T46	4892	24	0	0
T76	0	41	0	0
T77	4858	9	0	0
T79	5014	20	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	112	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2574	0	0
T29	2610	5	0	0
T42	10435	28	0	0
T43	0	54	0	0
T44	0	72	0	0
T45	1248	8	0	0
T46	4892	7	0	0
T76	0	48	0	0
T77	4858	1	0	0
T79	5014	21	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	81	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2523	0	0
T29	2610	12	0	0
T42	10435	7	0	0
T43	22890	41	0	0
T44	21538	77	0	0
T45	1248	9	0	0
T46	4892	41	0	0
T76	0	26	0	0
T78	6845	0	0	0
T79	5014	13	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	70	0	0
T112	0	5	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2520	0	0
T29	2610	11	0	0
T42	10435	19	0	0
T43	0	75	0	0
T44	0	67	0	0
T45	1248	3	0	0
T46	4892	30	0	0
T76	0	37	0	0
T77	4858	19	0	0
T79	5014	22	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	61	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2762	0	0
T29	2610	10	0	0
T42	10435	34	0	0
T43	0	54	0	0
T44	0	88	0	0
T45	1248	7	0	0
T46	4892	54	0	0
T76	0	50	0	0
T77	4858	1	0	0
T79	5014	22	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	78	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2683	0	0
T29	2610	24	0	0
T42	10435	8	0	0
T43	0	54	0	0
T44	0	84	0	0
T45	1248	1	0	0
T46	4892	33	0	0
T76	0	34	0	0
T77	4858	6	0	0
T79	5014	20	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	107	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2704	0	0
T29	2610	13	0	0
T42	10435	24	0	0
T43	0	31	0	0
T44	0	87	0	0
T45	1248	1	0	0
T46	4892	8	0	0
T76	0	45	0	0
T77	4858	3	0	0
T79	5014	17	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	72	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2523	0	0
T29	2610	18	0	0
T42	10435	16	0	0
T43	0	80	0	0
T44	0	85	0	0
T45	1248	6	0	0
T46	4892	3	0	0
T76	0	20	0	0
T77	4858	6	0	0
T79	5014	13	0	0
T81	967	0	0	0
T82	978	0	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	71	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10723435	2785	0	0
T29	2610	14	0	0
T42	10435	7	0	0
T43	22890	54	0	0
T44	21538	93	0	0
T45	1248	7	0	0
T46	4892	18	0	0
T76	0	45	0	0
T78	6845	0	0	0
T79	5014	16	0	0
T83	3873	0	0	0
T84	1372	0	0	0
T97	0	65	0	0
T112	0	14	0	0