Unified Coverage Report :: Module :: keymgr_dpe

Module : keymgr_dpe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.39	100.00	80.22	53.88		97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.39	100.00	80.22	53.88		97.83	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.39	100.00	80.22	53.88		97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.01	97.70	90.62	57.51	76.92	94.94	98.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_dpe_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	79.82	89.47	72.22			77.78
u_checks	100.00	100.00					100.00
u_ctrl	89.40	96.39	82.16	100.00	76.67	88.89	92.31
u_fault_alert	100.00			100.00
u_intr_op_done	93.75	100.00	75.00			100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_kmac_if	93.59	100.00	76.06	95.24	100.00	90.24	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_max_key_ver_regwen	67.84	78.95	57.89			66.67
u_op_err_alert	100.00			100.00
u_reg	98.17	98.11	95.65	100.00		97.07	100.00
u_reseed_ctrl	98.09	100.00	91.80	98.65		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	79.42	96.30	75.47		33.33	92.00	100.00
u_slot_policy_regwen	67.84	78.95	57.89			66.67
u_sw_binding_regwen	67.84	78.95	57.89			66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
ALWAYS	446	3	3	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	480	6	6	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
ALWAYS	757	5	5	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	815	0	0
CONT_ASSIGN	821	1	1	100.00
CONT_ASSIGN	822	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
228	1	1
229	1	1
231	1	1
232	1	1
264	2	2
268	1	1
283	1	1
337	1	1
339	1	1
357	1	1
368	1	1
369	1	1
370	1	1
417	1	1
418	1	1
419	1	1
441	1	1
446	1	1
447	1	1
448	1	1
457	1	1
459	1	1
470	1	1
472	1	1
480	1	1
481	1	1
483	1	1
489	1	1
493	1	1
494	1	1
502	1	1
503	1	1
506	1	1
508	1	1
513	1	1
544	1	1
545	1	1
546	1	1
547	1	1
548	1	1
549	1	1
550	1	1
551	1	1
552	1	1
557	1	1
558	1	1
559	1	1
560	1	1
563	1	1
567	1	1
568	1	1
570	1	1
581	1	1
586	1	1
587	1	1
706	1	1
707	1	1
708	1	1
710	1	1
711	1	1
712	1	1
713	1	1
714	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
747	1	1
749	1	1
752	1	1
753	1	1
757	1	1
758	1	1
759	1	1
761	1	1
762	1	1
767	1	1
784	1	1
815		unreachable
821	1	1
822	1	1

---

Cond Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Conditions	182	146	80.22
Logical	182	146	80.22
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T4,T5,T6

 LINE       208
 EXPRESSION (seed_en & ((~reg2hw.start.q)))
             ---1---   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       273
 EXPRESSION (otp_key_i.creator_root_key_share0_valid & otp_key_i.creator_root_key_share1_valid)
             -------------------1-------------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       347
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       368
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       369
 EXPRESSION (reg2hw.slot_policy_regwen.qe & ((~reg2hw.slot_policy_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       370
 EXPRESSION (reg2hw.max_key_ver_regwen.qe & ((~reg2hw.max_key_ver_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       417
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (slot_policy_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       419
 EXPRESSION (max_key_ver_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       489
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       503
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       503
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       508
 EXPRESSION (active_key_slot.valid ? ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}) : ({GenLfsrCopies {lfsr[31:0]}}))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       557
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       557
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       558
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       558
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       559
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       559
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       560
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       563
 EXPRESSION (adv_en & (active_key_slot.boot_stage == OwnerInt))
             ---1--   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       563
 SUB-EXPRESSION (active_key_slot.boot_stage == OwnerInt)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       568
 EXPRESSION (adv_en | gen_en)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       581
 EXPRESSION (((~key_vld)) | invalid_advance | ((~adv_dvalid[active_key_slot.boot_stage])))
             ------1-----   -------2-------   ---------------------3---------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Covered	T4,T5,T6
1	0	0	Not Covered

 LINE       586
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       587
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       659
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       659
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       666
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       666
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       749
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       753
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       753
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       767
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       784
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Totals	69	51	73.91
Total Bits	10582	5702	53.88
Total Bits 0->1	5291	2852	53.90
Total Bits 1->0	5291	2850	53.87

Ports	69	51	73.91
Port Bits	10582	5702	53.88
Port Bits 0->1	5291	2852	53.90
Port Bits 1->0	5291	2850	53.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T7,T8,T9	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T6,T10	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[9:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][7:5]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][8]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][9]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][14:10]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][15]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][17]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][18]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][21:19]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][22]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][26:23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][27]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][28]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][30:29]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][34:31]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][35]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][37:36]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][38]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][40:39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][41]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][51:42]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][52]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][57:53]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][58]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][59]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][63:61]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][64]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][65]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][67:66]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][68]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][69]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][72:70]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][73]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][76:74]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][77]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][78]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][83:79]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][84]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][86:85]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][87]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][93:88]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][94]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][95]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][96]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][100:97]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][101]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][105:102]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][106]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][107]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][108]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][111:109]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][112]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][114:113]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][115]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][116]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][117]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][118]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][121:119]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][122]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][123]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][125:124]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][127:126]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][129:128]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][130]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][132:131]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][133]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][134]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][135]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][137:136]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][138]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][140:139]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][141]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][143:142]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][144]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][145]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][148:146]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][149]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][151:150]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][152]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][155:153]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][156]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][157]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][158]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][161:159]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][162]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][166:163]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][167]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][169:168]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][170]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][177:171]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][178]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][184:179]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][185]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][189:186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][190]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][194:191]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][201:196]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][202]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][207:203]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][208]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][209]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][212:210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][213]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][216:214]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][217]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][218]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][219]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][221:220]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][222]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][224:223]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][225]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][226]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][227]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][228]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][229]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][230]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][232]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][233]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][235:234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][236]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][238:237]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][239]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[0][240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][244:241]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][245]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][251:246]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][252]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[0][254]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[0][255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][4:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][5]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][8:6]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][9]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][16:10]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][18:17]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][20:19]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][21]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][22]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][27:24]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][28]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][35:29]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][36]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][37]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][38]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][48:39]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][50]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[1][51]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][52]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][53]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][55:54]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][56]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][58:57]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][59]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][61]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][62]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][64:63]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][65]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][67:66]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][68]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][74:69]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][76]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][78:77]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][79]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][87:80]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][88]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[1][89]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][90]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][91]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][92]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][104:93]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][105]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][107:106]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][109:108]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][110]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][111]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][112]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][113]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][115:114]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][116]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][117]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][118]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][122:119]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][123]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][124]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][125]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][127:126]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][128]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][130:129]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][131]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][133:132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][134]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][137:135]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][138]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][143:139]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][144]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][145]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][146]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][147]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][155:148]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][156]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][160:157]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][161]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][165:162]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][166]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[1][171:167]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][172]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[1][178:173]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][179]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][182:180]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][183]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][184]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][185]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][193:186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][194]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][195]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][196]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][197]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][198]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][201:199]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][202]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][203]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][208:204]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][209]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][218:210]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][219]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][221:220]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][222]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][223]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][224]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][228:225]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][229]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][230]	Yes	Yes	T5,T6,T11	Yes	T5,T6,T11	OUTPUT
aes_key_o.key[1][231]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][238:232]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][239]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][241:240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][250:243]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1][252]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
aes_key_o.key[1][255:253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.valid	No	No		Yes	T4,T5,T6	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_key_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][1]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][6]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][7]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][10:8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][12:11]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][14:13]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][15]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][19]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][26:20]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][27]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][29:28]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][30]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][31]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][33:32]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][34]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][35]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][38:36]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][39]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][40]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][43:41]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][44]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][49:45]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][50]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][56:51]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][58:57]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][61:59]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][62]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][64:63]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][65]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][67:66]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][68]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][74:69]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][75]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][82:76]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][83]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][84]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][87:85]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][88]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][90:89]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][91]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][93:92]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][94]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][96:95]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][97]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][98]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][99]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][100]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][101]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][102]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][103]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][110:104]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][111]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][114:112]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][115]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][121:116]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][122]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][123]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][124]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][126:125]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][128:127]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][129]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][131:130]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][133:132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][134]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][138:135]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][139]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][148:140]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][149]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][154:150]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][155]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][156]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][157]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][159:158]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][160]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][166:161]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][169:167]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][170]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][172:171]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][174:173]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][175]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][176]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][177]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][178]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][179]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][180]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][181]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][182]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][183]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][184]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][185]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][190:186]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][191]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][192]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][193]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][195:194]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][197:196]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][198]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][200:199]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][201]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][202]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][203]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][204]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][206:205]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][212:207]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][213]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][224:214]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][225]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][228:226]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][229]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][230]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][233:231]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][234]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][236:235]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][237]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][238]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][239]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][241]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][244:242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][247:245]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][253:248]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][254]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][256]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][260:257]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][261]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][262]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][263]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][264]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][268:265]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][269]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][271:270]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][272]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][275:273]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][276]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][277]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][278]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][280:279]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][282:281]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][283]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][284]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][286:285]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][287]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][288]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][289]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][291:290]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][293:292]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][294]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][303:295]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][304]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][305]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][308:306]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][311:309]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][319:312]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][320]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][321]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][322]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][330:323]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][333:331]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][334]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][335]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][340:336]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][341]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][342]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[0][350:343]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][352:351]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][353]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[0][355:354]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][356]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][360:357]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][361]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][362]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][363]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][364]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][365]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][366]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][367]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[0][370:368]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][371]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][372]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[0][376:373]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[0][383:377]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][1]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][3]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][5]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][6]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][7]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][11:8]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][12]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][14:13]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][15]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][19]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][20]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][22:21]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][26:23]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][27]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][35:28]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][36]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][40:37]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][42:41]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][43]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][44]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][46:45]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][47]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][48]	Yes	Yes	T6,T10,T11	Yes	T6,T10,T11	OUTPUT
otbn_key_o.key[1][49]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][50]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][51]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][52]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
otbn_key_o.key[1][54:53]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][55]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][56]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][58:57]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][59]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][64:60]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][65]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][71:66]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][72]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][73]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][74]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][75]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][76]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][79:77]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][80]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][83:81]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][85:84]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][87:86]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][89:88]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][90]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][92:91]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][93]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][94]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][95]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][99:96]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][100]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][114:101]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][115]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][116]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][117]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][126:118]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][128:127]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][130:129]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][131]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][132]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][133]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][134]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][136:135]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][138:137]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][139]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][140]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][142:141]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][143]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][144]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][146:145]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][147]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][148]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][150:149]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][151]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][155:152]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][156]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][157]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][158]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][159]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][160]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][161]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][163:162]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][164]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][165]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][170:166]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][171]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][173:172]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][174]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][176:175]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][177]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][180:178]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][181]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][187:182]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][188]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][194:189]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][195]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][196]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][197]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][198]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][199]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][201:200]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][202]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][203]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][204]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][206:205]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][207]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][212:208]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][213]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][214]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][215]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][216]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][218:217]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][224:219]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][225]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][226]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][230:227]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][231]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][234:232]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][235]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][236]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][239:237]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][240]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][241]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][243:242]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][244]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][248:245]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][249]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][250]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][251]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][252]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][253]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][254]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][256:255]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][257]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][258]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][259]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][264:260]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][265]	Yes	Yes	T4,T5,T10	Yes	T4,T5,T10	OUTPUT
otbn_key_o.key[1][267:266]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][268]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][269]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][270]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][271]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][274:272]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][282:275]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][285:283]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][286]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][287]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][288]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][290:289]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][291]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][295:292]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][296]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][301:297]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][302]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][303]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][304]	Yes	Yes	T5,T10,T11	Yes	T5,T10,T11	OUTPUT
otbn_key_o.key[1][310:305]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][311]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][315:312]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][316]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][326:317]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][327]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][332:328]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][333]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][335:334]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][336]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][340:337]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][341]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][343:342]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][344]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][345]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][347:346]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][348]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][351:349]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][352]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][354:353]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][355]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][360:356]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][361]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][362]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][363]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][370:364]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][371]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][372]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][376:373]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][377]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][378]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.key[1][379]	Yes	Yes	T5,T6,T10	Yes	T5,T6,T10	OUTPUT
otbn_key_o.key[1][383:380]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_key_o.valid	No	No		Yes	T4,T5,T6	OUTPUT
kmac_data_o.last	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.ready	Yes	Yes	T1,T3,T5	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T2,T5,T6	INPUT
lc_keymgr_div_i[127:0]	No	No		No		INPUT
otp_key_i.owner_seed_valid	No	No		No		INPUT
otp_key_i.owner_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_seed_valid	No	No		No		INPUT
otp_key_i.creator_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	No	No		No		INPUT
otp_device_id_i[255:0]	No	No		No		INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_digest_i[0].valid	No	No		No		INPUT
rom_digest_i[0].data[255:0]	No	No		No		INPUT
rom_digest_i[1].valid	No	No		No		INPUT
rom_digest_i[1].data[255:0]	No	No		No		INPUT
intr_op_done_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	503	4	4	100.00
TERNARY	508	2	2	100.00
TERNARY	749	3	2	66.67
TERNARY	753	3	3	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	659	2	2	100.00
TERNARY	666	2	2	100.00
IF	757	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	503	((dest_sel == Aes)) ? 
-2-:	503	((dest_sel == Kmac)) ? 
-3-:	503	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	508	(active_key_slot.valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	749	(fault_errs) ? 
-2-:	749	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T8,T9
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	753	(op_errs) ? 
-2-:	753	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	659	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	666	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	757	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	104	104	0	0
AesKeyKnownO_A	7198797	7130330	0	0
AlertKnownO_A	7198797	7130330	0	0
ErrCntMatch_A	104	104	0	0
FaultCntMatch_A	104	104	0	0
FpvSecCmCtrlCntAlertCheck_A	7198797	90	0	0
FpvSecCmCtrlDataFsmCheck_A	7198797	90	0	0
FpvSecCmCtrlMainFsmCheck_A	7198797	90	0	0
FpvSecCmCtrlOpFsmCheck_A	7198797	90	0	0
FpvSecCmKmacIfCntAlertCheck_A	7198797	90	0	0
FpvSecCmKmacIfFsmCheck_A	7198797	90	0	0
FpvSecCmRegWeOnehotCheck_A	7198797	90	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	7198797	90	0	0
FpvSecCmSideloadCtrlFsmCheck_A	7198797	90	0	0
GenDataWidth_A	104	104	0	0
IntrKnownO_A	7198797	7130330	0	0
KeyWidthEqualityCheck_A	104	104	0	0
KmacDataKnownO_A	7160313	7091846	0	0
KmacKeyKnownO_A	7198797	7130330	0	0
KmacMaskCheck_A	104	104	0	0
LfsrWidth_A	104	104	0	0
OtbnKeyKnownO_A	7198797	7130330	0	0
OutputKeyDiff_A	104	104	0	0
TlAReadyKnownO_A	7198797	7130330	0	0
TlDValidKnownO_A	7198797	7130330	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	90	0	0
T7	100698	20	0	0
T8	140348	20	0	0
T9	53900	10	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	983	0	0	0
T27	145589	0	0	0
T28	54278	0	0	0
T29	747	0	0	0
T30	1175	0	0	0
T31	163449	0	0	0
T32	63888	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

KeyWidthEqualityCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7160313	7091846	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7198797	7130330	0	0
T1	1010	925	0	0
T2	1147	1058	0	0
T3	1101	1001	0	0
T4	26894	26842	0	0
T5	137357	137296	0	0
T6	464446	464392	0	0
T10	37133	37071	0	0
T17	1119	1046	0	0
T18	1359	1297	0	0
T19	1278	1203	0	0