Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8375077	9258	0	0
intr_enable_rd_A	8375077	1556	0	0
key_version_rd_A	8375077	1317	0	0
reseed_interval_regwen_rd_A	8375077	582	0	0
salt_0_rd_A	8375077	1351	0	0
salt_1_rd_A	8375077	1394	0	0
salt_2_rd_A	8375077	1304	0	0
salt_3_rd_A	8375077	1264	0	0
salt_4_rd_A	8375077	1426	0	0
salt_5_rd_A	8375077	1291	0	0
salt_6_rd_A	8375077	1222	0	0
salt_7_rd_A	8375077	1375	0	0
sideload_clear_rd_A	8375077	1279	0	0
slot_policy_rd_A	8375077	2035	0	0
sw_binding_0_rd_A	8375077	1334	0	0
sw_binding_1_rd_A	8375077	1297	0	0
sw_binding_2_rd_A	8375077	1229	0	0
sw_binding_3_rd_A	8375077	1347	0	0
sw_binding_4_rd_A	8375077	1202	0	0
sw_binding_5_rd_A	8375077	1310	0	0
sw_binding_6_rd_A	8375077	1286	0	0
sw_binding_7_rd_A	8375077	1285	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	9258	0	0
T21	24118	5	0	0
T22	2990	296	0	0
T23	1622	9	0	0
T35	16367	6	0	0
T36	0	5	0	0
T37	3513	327	0	0
T38	5185	312	0	0
T41	2182	115	0	0
T65	5624	0	0	0
T70	2303	24	0	0
T71	1498	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1556	0	0
T23	1622	2	0	0
T36	9943	0	0	0
T47	1227	6	0	0
T64	11112	37	0	0
T65	5624	11	0	0
T66	6559	0	0	0
T70	2303	4	0	0
T72	3491	4	0	0
T85	9504	51	0	0
T89	783	0	0	0
T101	0	6	0	0
T102	0	1	0	0
T103	0	10	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1317	0	0
T23	1622	3	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	35	0	0
T65	5624	24	0	0
T66	6559	0	0	0
T69	0	131	0	0
T70	2303	3	0	0
T71	1498	4	0	0
T72	3491	5	0	0
T85	9504	41	0	0
T101	0	8	0	0
T103	0	9	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	582	0	0
T23	1622	6	0	0
T36	9943	0	0	0
T42	0	7	0	0
T64	11112	0	0	0
T65	5624	12	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	18	0	0
T70	2303	1	0	0
T72	3491	0	0	0
T85	9504	44	0	0
T89	783	0	0	0
T103	0	6	0	0
T104	0	14	0	0
T105	0	15	0	0
T106	0	11	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1351	0	0
T23	1622	7	0	0
T36	9943	0	0	0
T64	11112	44	0	0
T65	5624	14	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	127	0	0
T70	2303	11	0	0
T72	3491	13	0	0
T85	9504	59	0	0
T89	783	0	0	0
T101	0	7	0	0
T103	0	9	0	0
T107	0	2	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1394	0	0
T23	1622	12	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	50	0	0
T65	5624	21	0	0
T66	6559	0	0	0
T69	0	130	0	0
T70	2303	5	0	0
T71	1498	1	0	0
T72	3491	0	0	0
T85	9504	34	0	0
T101	0	8	0	0
T103	0	13	0	0
T107	0	12	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1304	0	0
T23	1622	7	0	0
T36	9943	0	0	0
T64	11112	28	0	0
T65	5624	19	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	137	0	0
T70	2303	6	0	0
T72	3491	3	0	0
T85	9504	57	0	0
T89	783	0	0	0
T101	0	8	0	0
T103	0	15	0	0
T107	0	15	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1264	0	0
T23	1622	10	0	0
T36	9943	0	0	0
T38	5185	4	0	0
T41	2182	0	0	0
T64	11112	46	0	0
T65	5624	8	0	0
T70	2303	7	0	0
T71	1498	5	0	0
T72	3491	8	0	0
T85	9504	24	0	0
T101	0	9	0	0
T103	0	10	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1426	0	0
T23	1622	1	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	47	0	0
T65	5624	22	0	0
T66	6559	0	0	0
T69	0	134	0	0
T70	2303	4	0	0
T71	1498	5	0	0
T72	3491	0	0	0
T85	9504	99	0	0
T101	0	1	0	0
T103	0	11	0	0
T107	0	9	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1291	0	0
T23	1622	5	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	44	0	0
T65	5624	21	0	0
T66	6559	0	0	0
T69	0	173	0	0
T70	2303	11	0	0
T71	1498	3	0	0
T72	3491	0	0	0
T85	9504	36	0	0
T101	0	14	0	0
T103	0	8	0	0
T104	0	94	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1222	0	0
T23	1622	4	0	0
T36	9943	0	0	0
T38	5185	6	0	0
T41	2182	0	0	0
T64	11112	21	0	0
T65	5624	17	0	0
T70	2303	17	0	0
T71	1498	5	0	0
T72	3491	9	0	0
T85	9504	43	0	0
T101	0	8	0	0
T103	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1375	0	0
T23	1622	4	0	0
T36	9943	0	0	0
T64	11112	27	0	0
T65	5624	22	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	132	0	0
T70	2303	2	0	0
T72	3491	2	0	0
T85	9504	24	0	0
T89	783	0	0	0
T101	0	11	0	0
T103	0	4	0	0
T107	0	13	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1279	0	0
T23	1622	5	0	0
T36	9943	0	0	0
T64	11112	40	0	0
T65	5624	14	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	124	0	0
T70	2303	6	0	0
T72	3491	5	0	0
T85	9504	4	0	0
T89	783	0	0	0
T101	0	6	0	0
T103	0	9	0	0
T107	0	8	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	2035	0	0
T23	1622	6	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	75	0	0
T65	5624	13	0	0
T66	6559	0	0	0
T69	0	281	0	0
T70	2303	13	0	0
T71	1498	1	0	0
T72	3491	7	0	0
T85	9504	76	0	0
T101	0	8	0	0
T103	0	16	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1334	0	0
T23	1622	7	0	0
T36	9943	0	0	0
T38	5185	1	0	0
T41	2182	0	0	0
T64	11112	39	0	0
T65	5624	21	0	0
T69	0	146	0	0
T70	2303	3	0	0
T71	1498	5	0	0
T72	3491	0	0	0
T85	9504	25	0	0
T101	0	11	0	0
T103	0	12	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1297	0	0
T23	1622	7	0	0
T36	9943	0	0	0
T64	11112	30	0	0
T65	5624	18	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	116	0	0
T70	2303	2	0	0
T72	3491	3	0	0
T85	9504	52	0	0
T89	783	0	0	0
T101	0	7	0	0
T103	0	6	0	0
T107	0	12	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1229	0	0
T23	1622	6	0	0
T36	9943	0	0	0
T64	11112	33	0	0
T65	5624	34	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	97	0	0
T70	2303	1	0	0
T72	3491	0	0	0
T85	9504	22	0	0
T89	783	0	0	0
T101	0	5	0	0
T103	0	4	0	0
T104	0	72	0	0
T107	0	2	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1347	0	0
T36	9943	0	0	0
T38	5185	4	0	0
T41	2182	0	0	0
T64	11112	52	0	0
T65	5624	22	0	0
T66	6559	0	0	0
T69	0	156	0	0
T70	2303	0	0	0
T71	1498	4	0	0
T72	3491	0	0	0
T85	9504	26	0	0
T101	0	12	0	0
T103	0	7	0	0
T104	0	79	0	0
T107	0	9	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1202	0	0
T23	1622	4	0	0
T36	9943	0	0	0
T38	5185	3	0	0
T41	2182	0	0	0
T64	11112	38	0	0
T65	5624	13	0	0
T69	0	118	0	0
T70	2303	5	0	0
T71	1498	2	0	0
T72	3491	0	0	0
T85	9504	52	0	0
T101	0	11	0	0
T107	0	7	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1310	0	0
T23	1622	2	0	0
T36	9943	0	0	0
T64	11112	45	0	0
T65	5624	18	0	0
T66	6559	0	0	0
T67	2631	0	0	0
T69	0	121	0	0
T70	2303	9	0	0
T72	3491	3	0	0
T85	9504	35	0	0
T89	783	0	0	0
T101	0	12	0	0
T103	0	11	0	0
T107	0	15	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1286	0	0
T23	1622	4	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	46	0	0
T65	5624	22	0	0
T66	6559	0	0	0
T69	0	170	0	0
T70	2303	10	0	0
T71	1498	6	0	0
T72	3491	0	0	0
T85	9504	71	0	0
T101	0	6	0	0
T103	0	4	0	0
T107	0	8	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8375077	1285	0	0
T23	1622	3	0	0
T36	9943	0	0	0
T41	2182	0	0	0
T64	11112	18	0	0
T65	5624	21	0	0
T66	6559	0	0	0
T69	0	135	0	0
T70	2303	7	0	0
T71	1498	2	0	0
T72	3491	6	0	0
T85	9504	24	0	0
T101	0	11	0	0
T103	0	15	0	0