Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1072522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248077

1

T1

2370

T2

2975

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1174226	1			T1	8660		T2	4530		T3	1
values[0x0]	72368	1			T1	565		T2	728		T3	8
values[0x1]	74005	1			T1	530		T2	760		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	730715	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

589884

1

T1

4698

T2

3752

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4333	1			T1	54		T2	18		T5	5
valid_sources[0x01]	4256	1			T1	43		T2	46		T5	2
valid_sources[0x02]	4244	1			T1	41		T2	31		T5	2
valid_sources[0x03]	3958	1			T1	44		T2	23		T5	5
valid_sources[0x04]	4253	1			T1	31		T2	39		T5	2
valid_sources[0x05]	4003	1			T1	40		T2	37		T5	3
valid_sources[0x06]	4206	1			T1	42		T2	33		T15	2
valid_sources[0x07]	3910	1			T1	30		T2	11		T5	11
valid_sources[0x08]	4092	1			T1	45		T2	9		T6	9
valid_sources[0x09]	3997	1			T1	25		T2	24		T5	2
valid_sources[0x0a]	3896	1			T1	26		T2	19		T5	3
valid_sources[0x0b]	4200	1			T1	30		T2	29		T5	7
valid_sources[0x0c]	4035	1			T1	31		T2	18		T5	6
valid_sources[0x0d]	4113	1			T1	47		T2	9		T15	1
valid_sources[0x0e]	6094	1			T1	57		T2	21		T15	1
valid_sources[0x0f]	4016	1			T1	37		T2	22		T5	1
valid_sources[0x10]	3958	1			T1	42		T2	29		T5	2
valid_sources[0x11]	4269	1			T1	38		T2	16		T3	5
valid_sources[0x12]	4239	1			T1	29		T2	10		T5	16
valid_sources[0x13]	4155	1			T1	33		T2	17		T5	9
valid_sources[0x14]	4063	1			T1	36		T2	6		T5	1
valid_sources[0x15]	3866	1			T1	31		T2	40		T15	1
valid_sources[0x16]	8105	1			T1	40		T2	31		T5	3
valid_sources[0x17]	4409	1			T1	29		T2	28		T5	1
valid_sources[0x18]	4203	1			T1	35		T2	5		T19	28
valid_sources[0x19]	4090	1			T1	39		T2	21		T5	9
valid_sources[0x1a]	8035	1			T1	40		T2	27		T5	2
valid_sources[0x1b]	3954	1			T1	39		T2	11		T15	1
valid_sources[0x1c]	4169	1			T1	24		T2	15		T6	1
valid_sources[0x1d]	4442	1			T1	32		T2	33		T5	1
valid_sources[0x1e]	4135	1			T1	52		T2	21		T6	10
valid_sources[0x1f]	3885	1			T1	55		T2	12		T6	8
valid_sources[0x20]	4089	1			T1	34		T2	30		T5	2
valid_sources[0x21]	4024	1			T1	34		T2	22		T5	2
valid_sources[0x22]	4042	1			T1	45		T2	15		T5	7
valid_sources[0x23]	6850	1			T1	51		T2	27		T6	14
valid_sources[0x24]	4190	1			T1	46		T2	22		T5	8
valid_sources[0x25]	4088	1			T1	37		T2	39		T6	19
valid_sources[0x26]	3991	1			T1	45		T2	12		T15	5
valid_sources[0x27]	4116	1			T1	22		T2	22		T5	8
valid_sources[0x28]	4257	1			T1	33		T2	17		T5	2
valid_sources[0x29]	3930	1			T1	26		T2	9		T15	1
valid_sources[0x2a]	4100	1			T1	56		T2	16		T5	9
valid_sources[0x2b]	4239	1			T1	27		T2	34		T5	2
valid_sources[0x2c]	4129	1			T1	52		T2	17		T5	2
valid_sources[0x2d]	4262	1			T1	40		T2	44		T5	3
valid_sources[0x2e]	3942	1			T1	50		T2	45		T15	1
valid_sources[0x2f]	4257	1			T1	55		T2	26		T6	14
valid_sources[0x30]	4263	1			T1	36		T2	12		T5	3
valid_sources[0x31]	3868	1			T1	38		T2	11		T5	8
valid_sources[0x32]	4068	1			T1	31		T2	17		T5	2
valid_sources[0x33]	4167	1			T1	32		T2	29		T6	6
valid_sources[0x34]	4253	1			T1	38		T2	16		T5	11
valid_sources[0x35]	4922	1			T1	36		T2	14		T5	16
valid_sources[0x36]	3929	1			T1	30		T2	32		T15	1
valid_sources[0x37]	3855	1			T1	38		T2	38		T5	3
valid_sources[0x38]	19412	1			T1	38		T2	39		T4	15318
valid_sources[0x39]	3985	1			T1	26		T2	11		T5	13
valid_sources[0x3a]	4257	1			T1	46		T2	31		T5	9
valid_sources[0x3b]	4037	1			T1	36		T2	32		T6	10
valid_sources[0x3c]	7074	1			T1	30		T2	20		T5	2
valid_sources[0x3d]	4101	1			T1	43		T2	22		T5	3
valid_sources[0x3e]	4060	1			T1	28		T2	40		T5	1
valid_sources[0x3f]	3967	1			T1	47		T2	22		T5	3
valid_sources[0x40]	5871	1			T1	54		T2	12		T6	9
valid_sources[0x41]	4252	1			T1	33		T2	30		T5	6
valid_sources[0x42]	6260	1			T1	33		T2	24		T5	1
valid_sources[0x43]	5447	1			T1	49		T2	29		T15	2
valid_sources[0x44]	4045	1			T1	32		T2	31		T6	16
valid_sources[0x45]	3972	1			T1	35		T2	7		T5	6
valid_sources[0x46]	3924	1			T1	45		T2	24		T5	4
valid_sources[0x47]	4087	1			T1	47		T2	20		T5	1
valid_sources[0x48]	3823	1			T1	38		T2	24		T6	7
valid_sources[0x49]	4295	1			T1	47		T2	21		T5	16
valid_sources[0x4a]	4247	1			T1	34		T2	13		T5	6
valid_sources[0x4b]	4081	1			T1	30		T2	17		T5	2
valid_sources[0x4c]	6366	1			T1	45		T2	22		T5	3
valid_sources[0x4d]	6023	1			T1	40		T2	18		T5	2
valid_sources[0x4e]	3973	1			T1	44		T2	29		T5	6
valid_sources[0x4f]	4007	1			T1	34		T2	22		T6	9
valid_sources[0x50]	4291	1			T1	29		T2	22		T5	7
valid_sources[0x51]	4152	1			T1	39		T2	16		T5	4
valid_sources[0x52]	3989	1			T1	34		T2	10		T15	1
valid_sources[0x53]	3944	1			T1	27		T2	22		T5	5
valid_sources[0x54]	4235	1			T1	42		T2	27		T5	7
valid_sources[0x55]	4324	1			T1	33		T2	18		T5	11
valid_sources[0x56]	3977	1			T1	38		T2	10		T5	10
valid_sources[0x57]	4109	1			T1	33		T2	40		T5	2
valid_sources[0x58]	4110	1			T1	38		T2	22		T5	11
valid_sources[0x59]	4007	1			T1	29		T2	25		T3	6
valid_sources[0x5a]	4274	1			T1	32		T2	27		T15	1
valid_sources[0x5b]	4449	1			T1	31		T2	13		T6	20
valid_sources[0x5c]	3893	1			T1	46		T2	27		T5	8
valid_sources[0x5d]	4292	1			T1	53		T2	11		T15	1
valid_sources[0x5e]	4298	1			T1	26		T2	4		T5	5
valid_sources[0x5f]	4365	1			T1	47		T2	15		T5	5
valid_sources[0x60]	4226	1			T1	38		T2	31		T6	14
valid_sources[0x61]	6220	1			T1	37		T2	14		T17	26
valid_sources[0x62]	3927	1			T1	24		T2	10		T5	6
valid_sources[0x63]	3991	1			T1	47		T2	35		T5	12
valid_sources[0x64]	4105	1			T1	41		T2	34		T5	3
valid_sources[0x65]	4098	1			T1	44		T2	17		T5	4
valid_sources[0x66]	3976	1			T1	33		T2	16		T6	12
valid_sources[0x67]	3910	1			T1	32		T2	28		T6	13
valid_sources[0x68]	4261	1			T1	50		T2	14		T5	3
valid_sources[0x69]	4021	1			T1	42		T2	38		T5	11
valid_sources[0x6a]	7858	1			T1	58		T2	12		T6	8
valid_sources[0x6b]	3937	1			T1	36		T2	13		T5	5
valid_sources[0x6c]	5374	1			T1	31		T2	32		T15	1
valid_sources[0x6d]	4005	1			T1	42		T2	24		T15	1
valid_sources[0x6e]	4299	1			T1	38		T2	10		T5	2
valid_sources[0x6f]	4229	1			T1	43		T2	10		T5	11
valid_sources[0x70]	3907	1			T1	27		T2	32		T5	2
valid_sources[0x71]	3951	1			T1	42		T2	3		T5	13
valid_sources[0x72]	4147	1			T1	34		T2	48		T5	2
valid_sources[0x73]	4241	1			T1	47		T2	38		T15	4
valid_sources[0x74]	4279	1			T1	33		T2	35		T5	1
valid_sources[0x75]	7443	1			T1	40		T2	26		T8	3435
valid_sources[0x76]	4009	1			T1	35		T2	67		T5	2
valid_sources[0x77]	4043	1			T1	29		T2	16		T5	4
valid_sources[0x78]	5118	1			T1	26		T2	10		T4	1304
valid_sources[0x79]	3995	1			T1	48		T2	16		T5	5
valid_sources[0x7a]	4266	1			T1	50		T2	38		T5	8
valid_sources[0x7b]	4051	1			T1	25		T2	45		T5	16
valid_sources[0x7c]	6057	1			T1	36		T2	25		T5	13
valid_sources[0x7d]	4031	1			T1	36		T2	23		T5	6
valid_sources[0x7e]	4084	1			T1	39		T2	25		T15	3
valid_sources[0x7f]	4183	1			T1	27		T2	25		T5	2
valid_sources[0x80]	4205	1			T1	46		T2	9		T5	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135777

1

T1

1570

T2

1958

T3

1

values[0x0]

all_enables

biggest_size

59533

1

T1

451

T2

563

T3

4

values[0x1]

all_enables

biggest_size

52767

1

T1

349

T2

454

T4

369