Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	8902633	8766	0	0
intr_enable_rd_A	8902633	2237	0	0
key_version_rd_A	8902633	2005	0	0
reseed_interval_regwen_rd_A	8902633	938	0	0
salt_0_rd_A	8902633	2079	0	0
salt_1_rd_A	8902633	1995	0	0
salt_2_rd_A	8902633	2164	0	0
salt_3_rd_A	8902633	2176	0	0
salt_4_rd_A	8902633	2104	0	0
salt_5_rd_A	8902633	2119	0	0
salt_6_rd_A	8902633	2128	0	0
salt_7_rd_A	8902633	2193	0	0
sideload_clear_rd_A	8902633	2154	0	0
slot_policy_rd_A	8902633	2372	0	0
sw_binding_0_rd_A	8902633	2173	0	0
sw_binding_1_rd_A	8902633	2113	0	0
sw_binding_2_rd_A	8902633	2085	0	0
sw_binding_3_rd_A	8902633	2014	0	0
sw_binding_4_rd_A	8902633	2118	0	0
sw_binding_5_rd_A	8902633	2206	0	0
sw_binding_6_rd_A	8902633	2213	0	0
sw_binding_7_rd_A	8902633	2173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	8766	0	0
T21	6714	353	0	0
T22	20328	5	0	0
T23	10754	672	0	0
T30	12673	394	0	0
T31	0	2	0	0
T35	1732	17	0	0
T36	2741	340	0	0
T58	1939	39	0	0
T63	1193	1	0	0
T65	2085	0	0	0
T83	1302	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2237	0	0
T21	6714	3	0	0
T22	20328	64	0	0
T42	1044	9	0	0
T58	1939	0	0	0
T65	2085	0	0	0
T66	641	0	0	0
T67	2266	9	0	0
T70	1621	4	0	0
T72	631	0	0	0
T73	0	217	0	0
T74	5017	18	0	0
T84	0	17	0	0
T85	0	4	0	0
T86	0	10	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2005	0	0
T22	20328	23	0	0
T31	4295	0	0	0
T38	0	19	0	0
T60	21147	0	0	0
T62	10754	0	0	0
T63	1193	9	0	0
T67	2266	7	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	9	0	0
T73	0	243	0	0
T74	5017	17	0	0
T84	0	8	0	0
T87	0	6	0	0
T88	0	243	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	938	0	0
T21	6714	9	0	0
T30	12673	7	0	0
T38	0	12	0	0
T39	10083	0	0	0
T63	1193	1	0	0
T74	5017	12	0	0
T84	3218	13	0	0
T85	1113	0	0	0
T86	1035	0	0	0
T87	0	6	0	0
T89	0	12	0	0
T90	0	402	0	0
T91	0	13	0	0
T92	6458	0	0	0
T93	904	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2079	0	0
T21	6714	8	0	0
T22	20328	57	0	0
T30	12673	2	0	0
T32	7485	0	0	0
T63	1193	9	0	0
T70	1621	5	0	0
T73	73789	246	0	0
T74	5017	17	0	0
T75	21740	0	0	0
T84	0	19	0	0
T87	0	2	0	0
T88	0	231	0	0
T94	9144	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	1995	0	0
T22	20328	54	0	0
T30	12673	4	0	0
T32	7485	0	0	0
T38	0	24	0	0
T70	1621	3	0	0
T73	73789	254	0	0
T74	5017	36	0	0
T75	21740	0	0	0
T76	1583	0	0	0
T84	0	8	0	0
T88	0	218	0	0
T89	0	16	0	0
T94	9144	0	0	0
T95	0	410	0	0
T96	1860	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2164	0	0
T22	20328	39	0	0
T31	4295	0	0	0
T38	0	3	0	0
T60	21147	0	0	0
T62	10754	0	0	0
T63	1193	6	0	0
T67	2266	6	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	8	0	0
T73	73789	261	0	0
T84	0	3	0	0
T87	0	8	0	0
T88	0	212	0	0
T89	0	9	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2176	0	0
T21	6714	7	0	0
T22	20328	62	0	0
T30	12673	11	0	0
T31	4295	0	0	0
T60	21147	0	0	0
T67	2266	10	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	7	0	0
T73	0	290	0	0
T74	5017	32	0	0
T84	0	13	0	0
T87	0	8	0	0
T88	0	238	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2104	0	0
T22	20328	49	0	0
T31	4295	0	0	0
T38	0	14	0	0
T60	21147	0	0	0
T62	10754	0	0	0
T63	1193	6	0	0
T67	2266	2	0	0
T68	2199	0	0	0
T69	954	0	0	0
T73	73789	271	0	0
T74	5017	19	0	0
T84	0	16	0	0
T87	0	5	0	0
T88	0	215	0	0
T95	0	455	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2119	0	0
T21	6714	12	0	0
T22	20328	59	0	0
T32	7485	0	0	0
T38	0	10	0	0
T70	1621	8	0	0
T73	73789	267	0	0
T74	5017	19	0	0
T75	21740	0	0	0
T76	1583	0	0	0
T84	0	19	0	0
T87	0	12	0	0
T88	0	213	0	0
T89	0	3	0	0
T94	9144	0	0	0
T96	1860	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2128	0	0
T22	20328	42	0	0
T30	12673	1	0	0
T32	7485	0	0	0
T38	0	7	0	0
T63	1193	4	0	0
T70	1621	5	0	0
T73	73789	251	0	0
T74	5017	47	0	0
T75	21740	0	0	0
T76	1583	0	0	0
T84	0	8	0	0
T87	0	7	0	0
T88	0	211	0	0
T94	9144	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2193	0	0
T21	6714	3	0	0
T22	20328	55	0	0
T30	12673	1	0	0
T31	4295	0	0	0
T63	1193	1	0	0
T67	2266	3	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	6	0	0
T73	0	293	0	0
T74	5017	24	0	0
T87	0	7	0	0
T88	0	245	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2154	0	0
T22	20328	41	0	0
T30	12673	3	0	0
T31	4295	0	0	0
T60	21147	0	0	0
T63	1193	1	0	0
T67	2266	3	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	6	0	0
T73	0	265	0	0
T74	5017	9	0	0
T84	0	18	0	0
T87	0	4	0	0
T88	0	236	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2372	0	0
T22	20328	87	0	0
T30	12673	9	0	0
T31	4295	0	0	0
T38	0	17	0	0
T60	21147	0	0	0
T62	10754	0	0	0
T67	2266	1	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	8	0	0
T73	0	250	0	0
T74	5017	20	0	0
T84	0	7	0	0
T87	0	12	0	0
T88	0	235	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2173	0	0
T22	20328	42	0	0
T31	4295	0	0	0
T38	0	27	0	0
T60	21147	0	0	0
T62	10754	0	0	0
T63	1193	9	0	0
T67	2266	3	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	8	0	0
T73	0	213	0	0
T74	5017	36	0	0
T84	0	6	0	0
T87	0	2	0	0
T88	0	231	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2113	0	0
T21	6714	1	0	0
T22	20328	26	0	0
T30	12673	20	0	0
T31	4295	0	0	0
T63	1193	1	0	0
T67	2266	6	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	8	0	0
T73	0	224	0	0
T74	5017	40	0	0
T84	0	15	0	0
T87	0	20	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2085	0	0
T21	6714	2	0	0
T22	20328	44	0	0
T31	4295	0	0	0
T38	0	16	0	0
T60	21147	0	0	0
T63	1193	7	0	0
T67	2266	4	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	3	0	0
T73	0	221	0	0
T74	5017	35	0	0
T84	0	21	0	0
T88	0	244	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2014	0	0
T21	6714	8	0	0
T22	20328	49	0	0
T30	12673	8	0	0
T32	7485	0	0	0
T63	1193	4	0	0
T70	1621	1	0	0
T73	73789	259	0	0
T74	5017	4	0	0
T75	21740	0	0	0
T84	0	8	0	0
T87	0	4	0	0
T88	0	193	0	0
T94	9144	0	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2118	0	0
T21	6714	14	0	0
T22	20328	26	0	0
T32	7485	0	0	0
T38	0	22	0	0
T63	1193	6	0	0
T70	1621	5	0	0
T73	73789	270	0	0
T74	5017	10	0	0
T75	21740	0	0	0
T76	1583	0	0	0
T84	0	7	0	0
T87	0	4	0	0
T88	0	216	0	0
T94	9144	0	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2206	0	0
T22	20328	31	0	0
T30	12673	5	0	0
T31	4295	0	0	0
T60	21147	0	0	0
T63	1193	7	0	0
T67	2266	4	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	5	0	0
T73	0	274	0	0
T74	5017	31	0	0
T84	0	19	0	0
T87	0	16	0	0
T88	0	206	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2213	0	0
T21	6714	14	0	0
T22	20328	52	0	0
T31	4295	0	0	0
T60	21147	0	0	0
T63	1193	2	0	0
T67	2266	6	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	1	0	0
T73	0	214	0	0
T74	5017	43	0	0
T84	0	7	0	0
T87	0	6	0	0
T88	0	230	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8902633	2173	0	0
T21	6714	16	0	0
T22	20328	41	0	0
T30	12673	10	0	0
T31	4295	0	0	0
T60	21147	0	0	0
T67	2266	4	0	0
T68	2199	0	0	0
T69	954	0	0	0
T70	1621	2	0	0
T73	0	235	0	0
T74	5017	28	0	0
T84	0	8	0	0
T87	0	5	0	0
T88	0	186	0	0