Unified Coverage Report :: Module :: keymgr_data_en_state

Module : keymgr_data_en_state

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.11	90.00	50.00		77.78	77.78	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_data_en_state.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_data_en	79.11	90.00	50.00		77.78	77.78	100.00

---

Module Instance : tb.dut.u_ctrl.u_data_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.11	90.00	50.00		77.78	77.78	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.02	92.31	50.00		77.78	80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.05	96.12	87.05		61.54	89.83	85.71	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_data_en_state

	Line No.	Total	Covered	Percent
TOTAL		30	27	90.00
ALWAYS	69	3	3	100.00
ALWAYS	79	27	24	88.89

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_data_en_state.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_data_en_state.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	3	3
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE
98	1	1
99	1	1
100	1	1
101	1	1
102	0	1
			MISSING_ELSE
107	1	1
108	1	1
109	1	1
110	1	1
111	0	1
			MISSING_ELSE
116	1	1
117	1	1
			MISSING_ELSE
122	1	1
123	1	1
			==> MISSING_ELSE

---

Cond Coverage for Module : keymgr_data_en_state

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (id_en_i || gen_en_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Unreachable

---

FSM Coverage for Module : keymgr_data_en_state

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	7	77.78
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlDataDis	87	Covered	T3,T4,T5
StCtrlDataHwEn	89	Covered	T3,T4,T5
StCtrlDataIdle	123	Covered	T1,T2,T3
StCtrlDataSwEn	91	Covered	T3,T4,T5
StCtrlDataWait	100	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
StCtrlDataDis->StCtrlDataWait	117	Covered	T3,T4,T5
StCtrlDataHwEn->StCtrlDataDis	102	Not Covered
StCtrlDataHwEn->StCtrlDataWait	100	Covered	T3,T4,T5
StCtrlDataIdle->StCtrlDataDis	87	Covered	T3,T4,T5
StCtrlDataIdle->StCtrlDataHwEn	89	Covered	T3,T4,T5
StCtrlDataIdle->StCtrlDataSwEn	91	Covered	T3,T4,T5
StCtrlDataSwEn->StCtrlDataDis	111	Not Covered
StCtrlDataSwEn->StCtrlDataWait	109	Covered	T3,T4,T5
StCtrlDataWait->StCtrlDataIdle	123	Covered	T3,T4,T5

---

Branch Coverage for Module : keymgr_data_en_state

	Line No.	Total	Covered	Percent
Branches		18	14	77.78
IF	69	2	2	100.00
CASE	83	16	12	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_data_en_state.sv' or '../src/lowrisc_ip_keymgr_common_0.1/rtl/keymgr_data_en_state.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	83	case (state_q)
-2-:	86	if (adv_en_i)
-3-:	88	if (((id_en_i || gen_en_i) && prim_mubi_pkg::mubi4_test_true_strict(hw_sel_i)))
-4-:	90	if (((id_en_i || gen_en_i) && prim_mubi_pkg::mubi4_test_false_strict(hw_sel_i)))
-5-:	92	if ((id_en_i || gen_en_i))
-6-:	99	if (op_done_i)
-7-:	101	if ((adv_en_i || prim_mubi_pkg::mubi4_test_false_loose(hw_sel_i)))
-8-:	108	if (op_done_i)
-9-:	110	if ((adv_en_i || prim_mubi_pkg::mubi4_test_true_loose(hw_sel_i)))
-10-:	116	if (op_done_i)
-11-:	122	if ((!op_start_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StCtrlDataIdle	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDataIdle	0	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDataIdle	0	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDataIdle	0	0	0	1	-	-	-	-	-	-	Not Covered
StCtrlDataIdle	0	0	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDataHwEn	-	-	-	-	1	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDataHwEn	-	-	-	-	0	1	-	-	-	-	Not Covered
StCtrlDataHwEn	-	-	-	-	0	0	-	-	-	-	Covered	T3,T4,T5
StCtrlDataSwEn	-	-	-	-	-	-	1	-	-	-	Covered	T3,T4,T5
StCtrlDataSwEn	-	-	-	-	-	-	0	1	-	-	Not Covered
StCtrlDataSwEn	-	-	-	-	-	-	0	0	-	-	Covered	T3,T4,T5
StCtrlDataDis	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T5
StCtrlDataDis	-	-	-	-	-	-	-	-	0	-	Covered	T3,T4,T5
StCtrlDataWait	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
StCtrlDataWait	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

---

Assert Coverage for Module : keymgr_data_en_state

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	7236189	7167592	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7236189	7167592	0	0
T1	1202	1126	0	0
T2	1059	959	0	0
T3	269503	269441	0	0
T4	56399	56317	0	0
T5	90729	90653	0	0
T9	62724	62652	0	0
T16	1353	1267	0	0
T17	1598	1498	0	0
T18	823	742	0	0
T19	1172	1103	0	0