Unified Coverage Report :: Module :: keymgr_dpe_ctrl

Module : keymgr_dpe_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.05	96.12	87.05		61.54	89.83	85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	84.05	96.12	87.05		61.54	89.83	85.71

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.05	96.12	87.05		61.54	89.83	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40	96.39	82.16	100.00	76.67	88.89	92.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.39	100.00	80.22	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_data_en	80.02	92.31	50.00		77.78	80.00	100.00
u_err	79.62	96.08	62.79			80.00
u_hw_sel	100.00	100.00				100.00	100.00
u_op_state	93.33	100.00	66.67		100.00	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
TOTAL		129	124	96.12
ALWAYS	93	4	4	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	220	3	3	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
ALWAYS	246	3	3	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	271	22	22	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	388	3	3	100.00
ALWAYS	395	47	42	89.36
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
ALWAYS	560	5	5	100.00
CONT_ASSIGN	618	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	644	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
ALWAYS	751	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
97	1	1
99	1	1
103	1	1
123	1	1
132	1	1
133	1	1
134	1	1
149	1	1
150	1	1
151	1	1
152	1	1
166	1	1
171	1	1
177	1	1
179	1	1
194	1	1
202	1	1
213	1	1
220	1	1
221	1	1
223	1	1
230	1	1
235	1	1
238	2	2
246	1	1
248	1	1
250	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
264	1	1
271	1	1
273	1	1
279	1	1
280	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
295	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
317	1	1
318	1	1
320	1	1
330	1	1
332	1	1
333	1	1
334	1	1
371	1	1
385	1	1
388	3	3
395	1	1
402	1	1
405	1	1
406	1	1
409	1	1
412	1	1
415	1	1
418	1	1
422	1	1
424	1	1
429	1	1
432	1	1
433	1	1
434	1	1
435	1	1
			MISSING_ELSE
441	1	1
445	1	1
446	1	1
447	0	1
448	1	1
449	1	1
			MISSING_ELSE
458	1	1
462	1	1
463	1	1
464	0	1
465	1	1
466		unreachable
467		unreachable
			MISSING_ELSE
474	1	1
478	1	1
480	1	1
481	0	1
483	1	1
490	1	1
493	1	1
497	1	1
498	0	1
499	1	1
500	1	1
			MISSING_ELSE
510	1	1
513	1	1
515	1	1
517	1	1
521	1	1
522	1	1
531	1	1
533	1	1
534	0	1
			MISSING_ELSE
541	1	1
553	1	1
554	1	1
560	1	1
561	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
618	1	1
623	1	1
626	1	1
630	1	1
637	1	1
641	1	1
644	1	1
646	1	1
652	1	1
657	1	1
751	3	3

---

Cond Coverage for Module : keymgr_dpe_ctrl

	Total	Covered	Percent
Conditions	193	168	87.05
Logical	193	168	87.05
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION ((op_i == OpDpeGenSwOut) | (op_i == OpDpeGenHwOut))
             -----------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       123
 SUB-EXPRESSION (op_i == OpDpeGenSwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       123
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (op_start_i & (op_i == OpDpeAdvance) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       132
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       133
 EXPRESSION (op_start_i & (op_i == OpDpeGenHwOut) & en_i)
             -----1----   -----------2-----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       133
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       134
 EXPRESSION (op_start_i & (op_i == OpDpeDisable) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       134
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       149
 EXPRESSION (op_req & (op_i == OpDpeAdvance))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       149
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       150
 EXPRESSION (op_req & gen_key_op)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (op_req & (op_i == OpDpeErase))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       151
 SUB-EXPRESSION (op_i == OpDpeErase)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (op_req & (op_i == OpDpeDisable))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       152
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       166
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T5

 LINE       194
 EXPRESSION (wipe_req ? SlotWipeAll : ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       194
 SUB-EXPRESSION ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel))
                 --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       194
 SUB-EXPRESSION (state_q == StCtrlDpeRandom)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       194
 SUB-EXPRESSION ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       194
 SUB-EXPRESSION (init_o & en_i & root_key_i.valid)
                 ---1--   --2-   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       202
 EXPRESSION 
 Number  Term
      1  (op_update & op_fault_err) ? SlotWipeAll : ((op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       202
 SUB-EXPRESSION (op_update & op_fault_err)
                 ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       202
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION (op_update & dis_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION (op_update & (op_err | fsm_at_disabled))
                 ----1----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION (op_err | fsm_at_disabled)
                 ---1--   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION (op_update & adv_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)
                 -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       202
 SUB-EXPRESSION (op_update & erase_req)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       213
 EXPRESSION (random_req | fsm_at_disabled | fsm_at_invalid | wipe_req)
             -----1----   -------2-------   -------3------   ----4---

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T6,T7,T8
0	0	1	0	Covered	T6,T7,T8
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Covered	T3,T4,T5

 LINE       230
 EXPRESSION (adv_req || gen_req)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       235
 EXPRESSION (active_key_slot_o.valid && ((!invalid_op)) && (adv_req || gen_req))
             -----------1-----------    -------2-------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       235
 SUB-EXPRESSION (adv_req || gen_req)
                 ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (release_real_key ? active_key_slot_o.key[0] : ({EntropyRounds {entropy_i[0]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       238
 EXPRESSION (release_real_key ? active_key_slot_o.key[1] : ({EntropyRounds {entropy_i[1]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       260
 EXPRESSION (op_ack & gen_key_op & ((~invalid_op)))
             ---1--   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       261
 EXPRESSION (update_sel == SlotWipeAll)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       346
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       346
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       371
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       371
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       429
 EXPRESSION (op_start_i & (((~en_i)) | (en_i & (op_i != OpDpeAdvance))))
             -----1----   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       429
 SUB-EXPRESSION (((~en_i)) | (en_i & (op_i != OpDpeAdvance)))
                 ----1----   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (en_i & (op_i != OpDpeAdvance))
                 --1-   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (op_i != OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Unreachable	T3,T4,T5

 LINE       480
 EXPRESSION (((!en_i)) | inv_state | ((~root_key_i.valid)))
             ----1----   ----2----   ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       493
 EXPRESSION (invalid_advance | invalid_erase | invalid_gen | (((~en_i)) & op_start_i))
             -------1-------   ------2------   -----3-----   ------------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Not Covered
1	0	0	0	Covered	T3,T4,T5

 LINE       493
 SUB-EXPRESSION (((~en_i)) & op_start_i)
                 ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       497
 EXPRESSION (((!en_i)) | inv_state)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       553
 EXPRESSION (state_q == StCtrlDpeDisabled)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       554
 EXPRESSION (state_q == StCtrlDpeInvalid)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       565
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       637
 EXPRESSION (active_slot_policy.retain_parent ? ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid) : (slot_src_sel_i != slot_dst_sel_i))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       637
 SUB-EXPRESSION ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid)
                 -----------------1----------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Not Covered

 LINE       637
 SUB-EXPRESSION (slot_src_sel_i == slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       637
 SUB-EXPRESSION (slot_src_sel_i != slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       641
 EXPRESSION (adv_req & (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent))
             ---1---   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       641
 SUB-EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
                 ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Not Covered

 LINE       644
 EXPRESSION (erase_req & ((~destination_slot_valid)))
             ----1----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       646
 EXPRESSION (gen_req & (((~active_key_slot_o.valid)) | ((~key_version_vld_o))))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       646
 SUB-EXPRESSION (((~active_key_slot_o.valid)) | ((~key_version_vld_o)))
                 --------------1-------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       652
 EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
             ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Not Covered

 LINE       659
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Not Covered

---

FSM Coverage for Module : keymgr_dpe_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	13	8	61.54
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlDpeAvailable	483	Covered	T3,T4,T5
StCtrlDpeDisabled	522	Covered	T3,T4,T5
StCtrlDpeDisabling	500	Covered	T3,T4,T5
StCtrlDpeEntropyReseed	435	Covered	T3,T4,T5
StCtrlDpeInvalid	433	Covered	T6,T7,T8
StCtrlDpeRandom	449	Covered	T3,T4,T5
StCtrlDpeReset	94	Covered	T1,T2,T3
StCtrlDpeRootKey	467	Covered	T3,T4,T5
StCtrlDpeWipe	498	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
StCtrlDpeAvailable->StCtrlDpeDisabling	500	Covered	T3,T4,T5
StCtrlDpeAvailable->StCtrlDpeWipe	498	Not Covered
StCtrlDpeDisabled->StCtrlDpeWipe	534	Not Covered
StCtrlDpeDisabling->StCtrlDpeDisabled	522	Covered	T3,T4,T5
StCtrlDpeEntropyReseed->StCtrlDpeInvalid	447	Not Covered
StCtrlDpeEntropyReseed->StCtrlDpeRandom	449	Covered	T3,T4,T5
StCtrlDpeRandom->StCtrlDpeInvalid	464	Not Covered
StCtrlDpeRandom->StCtrlDpeRootKey	467	Covered	T3,T4,T5
StCtrlDpeReset->StCtrlDpeEntropyReseed	435	Covered	T3,T4,T5
StCtrlDpeReset->StCtrlDpeInvalid	433	Covered	T6,T7,T8
StCtrlDpeRootKey->StCtrlDpeAvailable	483	Covered	T3,T4,T5
StCtrlDpeRootKey->StCtrlDpeInvalid	481	Not Covered
StCtrlDpeWipe->StCtrlDpeInvalid	517	Covered	T6,T7,T8

---

Branch Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
Branches		59	53	89.83
TERNARY	194	4	4	100.00
TERNARY	202	6	5	83.33
TERNARY	371	2	2	100.00
TERNARY	637	2	2	100.00
TERNARY	238	2	2	100.00
TERNARY	238	2	2	100.00
CASE	93	4	4	100.00
IF	220	2	2	100.00
IF	246	2	2	100.00
CASE	273	6	6	100.00
IF	388	2	2	100.00
CASE	424	19	14	73.68
IF	561	4	4	100.00
IF	751	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	194	(wipe_req) ? 
-2-:	194	((state_q == StCtrlDpeRandom)) ? 
-3-:	194	(((init_o & en_i) & root_key_i.valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	((op_update & op_fault_err)) ? 
-2-:	202	((op_update & dis_req)) ? 
-3-:	202	((op_update & (op_err | fsm_at_disabled))) ? 
-4-:	202	((op_update & adv_req)) ? 
-5-:	202	((op_update & erase_req)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Covered	T3,T4,T5
0	0	1	-	-	Covered	T3,T4,T5
0	0	0	1	-	Covered	T3,T4,T5
0	0	0	0	1	Covered	T3,T4,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	637	(active_slot_policy.retain_parent) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	case (state_q)

Branches:

-1-	Status	Tests
StCtrlDpeReset StCtrlDpeEntropyReseed StCtrlDpeRandom StCtrlDpeRootKey	Covered	T1,T2,T3
StCtrlDpeAvailable	Covered	T3,T4,T5
StCtrlDpeWipe StCtrlDpeDisabling StCtrlDpeDisabled	Covered	T3,T4,T5
default	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	220	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	case (update_sel)

Branches:

-1-	Status	Tests
SlotDestRandomize	Covered	T3,T4,T5
SlotLoadRoot	Covered	T3,T4,T5
SlotLoadFromKmac	Covered	T3,T4,T5
SlotErase	Covered	T3,T4,T5
SlotWipeAll SlotWipeInternalOnly	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	388	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	424	case (state_q)
-2-:	432	if (inv_state)
-3-:	434	if (advance_cmd)
-4-:	446	if ((!en_i))
-5-:	448	if (prng_reseed_ack_i)
-6-:	463	if ((!en_i))
-7-:	465	if ((int'(cnt) == (EntropyRounds - 1)))
-8-:	480	if ((((!en_i) | inv_state) | (~root_key_i.valid)))
-9-:	497	if (((!en_i) | inv_state))
-10-:	499	if (disable_cmd)
-11-:	533	if ((!en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StCtrlDpeReset	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StCtrlDpeReset	0	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeReset	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDpeEntropyReseed	-	-	1	-	-	-	-	-	-	-	Not Covered
StCtrlDpeEntropyReseed	-	-	0	1	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeEntropyReseed	-	-	0	0	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeRandom	-	-	-	-	1	-	-	-	-	-	Not Covered
StCtrlDpeRandom	-	-	-	-	0	1	-	-	-	-	Unreachable	T3,T4,T5
StCtrlDpeRandom	-	-	-	-	0	0	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeRootKey	-	-	-	-	-	-	1	-	-	-	Not Covered
StCtrlDpeRootKey	-	-	-	-	-	-	0	-	-	-	Covered	T3,T4,T5
StCtrlDpeAvailable	-	-	-	-	-	-	-	1	-	-	Not Covered
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
StCtrlDpeWipe	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StCtrlDpeDisabling	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	1	Not Covered
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
StCtrlDpeInvalid	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	561	if (op_done_o)
-2-:	565	((|{error_o, fault_o})) ? 
-3-:	566	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T4,T5
1	0	-	Covered	T3,T4,T5
0	-	1	Covered	T3,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	751	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	7192409	9177	0	0
DataEnDis_A	7118919	8727	0	0
DataEn_A	7118919	3716212	0	0
LoadKey_A	7162699	5347857	0	0
SameErrCnt_A	103	103	0	0
SecCmCFILinear_A	7236189	0	0	291
u_state_regs_A	7236189	7167592	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7192409	9177	0	0
T3	269503	153	0	0
T4	56399	174	0	0
T5	90729	182	0	0
T9	62724	160	0	0
T10	0	198	0	0
T11	0	182	0	0
T12	0	192	0	0
T13	0	200	0	0
T14	0	177	0	0
T15	0	205	0	0
T16	1353	0	0	0
T17	1598	0	0	0
T18	823	0	0	0
T19	1172	0	0	0
T20	1169	0	0	0
T21	1234	0	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7118919	8727	0	0
T3	269503	153	0	0
T4	56399	174	0	0
T5	90729	182	0	0
T9	62724	160	0	0
T10	0	198	0	0
T11	0	182	0	0
T12	0	192	0	0
T13	0	200	0	0
T14	0	177	0	0
T15	0	205	0	0
T16	1353	0	0	0
T17	1598	0	0	0
T18	823	0	0	0
T19	1172	0	0	0
T20	1169	0	0	0
T21	1234	0	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7118919	3716212	0	0
T3	269503	174088	0	0
T4	56399	9053	0	0
T5	90729	36788	0	0
T9	62724	21840	0	0
T10	0	9508	0	0
T11	0	1974	0	0
T12	0	9562	0	0
T13	0	2198	0	0
T14	0	12493	0	0
T15	0	433988	0	0
T16	1353	0	0	0
T17	1598	0	0	0
T18	823	0	0	0
T19	1172	0	0	0
T20	1169	0	0	0
T21	1234	0	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7162699	5347857	0	0
T3	269503	260353	0	0
T4	56399	11733	0	0
T5	90729	53532	0	0
T9	62724	30406	0	0
T10	0	12529	0	0
T11	0	3184	0	0
T12	0	12237	0	0
T13	0	3440	0	0
T14	0	17328	0	0
T15	0	619291	0	0
T16	1353	0	0	0
T17	1598	0	0	0
T18	823	0	0	0
T19	1172	0	0	0
T20	1169	0	0	0
T21	1234	0	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7236189	0	0	291

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7236189	7167592	0	0
T1	1202	1126	0	0
T2	1059	959	0	0
T3	269503	269441	0	0
T4	56399	56317	0	0
T5	90729	90653	0	0
T9	62724	62652	0	0
T16	1353	1267	0	0
T17	1598	1498	0	0
T18	823	742	0	0
T19	1172	1103	0	0