KEYMGR_DPE Simulation Results

Saturday March 23 2024 19:02:16 UTC

GitHub Revision: `d638842535`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2621884165

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.459m	26.334ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.190s	324.192us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.420s	93.674us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	18.810s	2.288ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	8.470s	444.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.170s	98.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.420s	93.674us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.470s	444.939us	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	0.990s	13.680us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.000s	18.557us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.110s	116.461us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.110s	116.461us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.190s	324.192us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	93.674us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.470s	444.939us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.230s	305.233us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.190s	324.192us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	93.674us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.470s	444.939us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.230s	305.233us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	19.330s	1.276ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.250s	905.011us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.630s	168.333us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.630s	168.333us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.630s	168.333us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.630s	168.333us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.560s	767.651us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	19.330s	1.276ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	19.330s	1.276ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			308	310	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.28	97.70	90.58	57.52	76.92	94.94	98.34	17.96

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_dpe_smoke has 1 failures.
  - 0.keymgr_dpe_smoke.1755875205
    Line 1117, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/0.keymgr_dpe_smoke/latest/run.log
```
  UVM_ERROR @ 589266856 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 589266856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:

Test keymgr_dpe_smoke has 1 failures.

15.keymgr_dpe_smoke.1107474112
Line 3248, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/15.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 519347092 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hb85a3c6af0f6d95bda502cccabd5ed46daf477eb725c7370206911b9ff181817d0b1541995c05863ceb3fbb04421dde30a21173822dd55d9f65604df01d43e85 vs. act 'h0
  UVM_INFO @ 519347092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---