KEYMGR_DPE Simulation Results

Saturday March 02 2024 20:02:25 UTC

GitHub Revision: `2f1cc9b27a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2863389695

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	4.119m	21.576ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.370s	440.448us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.250s	41.734us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	12.560s	898.014us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	8.080s	221.949us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.220s	105.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.250s	41.734us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.080s	221.949us	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	1.040s	22.457us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.000s	148.479us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.100s	619.066us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.100s	619.066us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.370s	440.448us	5	5	100.00
		keymgr_dpe_csr_rw	1.250s	41.734us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.080s	221.949us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.670s	443.361us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.370s	440.448us	5	5	100.00
		keymgr_dpe_csr_rw	1.250s	41.734us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.080s	221.949us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.670s	443.361us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	18.120s	5.651ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.730s	259.956us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.990s	232.172us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.990s	232.172us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.990s	232.172us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.990s	232.172us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	8.790s	1.005ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	18.120s	5.651ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	18.120s	5.651ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			308	310	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.25	97.70	90.49	57.52	76.92	94.94	98.34	17.82

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act *

has 2 failures:

Test keymgr_dpe_smoke has 2 failures.

3.keymgr_dpe_smoke.822474376
Line 2549, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/3.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 2210173578 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h611b61e7ae42599fab55dc6e42d15aae19cb87cd45ccb15b7714eb9e846e0eb104f575fba3beb42b00c5ff41c5b32e7691c5b4a4db53192f15401ef6ad7453ce vs. act 'h0
  UVM_INFO @ 2210173578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_dpe_smoke.2567330016
Line 3139, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/7.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 720702349 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h4fc605b395e97a12c0b56c40209c1b2b4f564fd02d4f645e357665fe553605903a09f5009082e29da7653473e800ea5c88e1ea36f96cdfa5aababa7b22541dcb vs. act 'h0
  UVM_INFO @ 720702349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---