Unified Coverage Report :: Module :: keymgr_dpe

Module : keymgr_dpe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.32	100.00	79.89	53.88		97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.32	100.00	79.89	53.88		97.83	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.32	100.00	79.89	53.88		97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.98	97.60	90.55	57.52	76.92	94.97	98.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_sw_assigns[0].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[0].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[0].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[1].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[1].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[1].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[2].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[2].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[2].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[3].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[3].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[3].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[4].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[4].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[4].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[5].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[5].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[5].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[6].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[6].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[6].u_prim_buf_share1_de	100.00	100.00
gen_sw_assigns[7].u_mubi_buf	100.00	100.00					100.00
gen_sw_assigns[7].u_prim_buf_share0_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share0_de	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_d	100.00	100.00
gen_sw_assigns[7].u_prim_buf_share1_de	100.00	100.00
keymgr_dpe_csr_assert	100.00						100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_cfgen	79.82	89.47	72.22			77.78
u_checks	100.00	100.00					100.00
u_ctrl	89.37	95.49	82.38	100.00	76.67	89.38	92.31
u_fault_alert	100.00			100.00
u_intr_op_done	93.75	100.00	75.00			100.00	100.00
u_key_valid_sync	100.00	100.00				100.00
u_kmac_if	93.59	100.00	76.06	95.24	100.00	90.24	100.00
u_lc_keymgr_en_sync	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_max_key_ver_regwen	67.84	78.95	57.89			66.67
u_op_err_alert	100.00			100.00
u_reg	98.14	98.11	95.53	100.00		97.07	100.00
u_reseed_ctrl	98.44	100.00	92.19	100.00		100.00	100.00
u_seed_anchor	0.00	0.00
u_sideload_ctrl	79.42	96.30	75.47		33.33	92.00	100.00
u_slot_policy_regwen	67.84	78.95	57.89			66.67
u_sw_binding_regwen	67.84	78.95	57.89			66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
ALWAYS	447	3	3	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
ALWAYS	481	6	6	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
ALWAYS	758	5	5	100.00
CONT_ASSIGN	768	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
CONT_ASSIGN	816	0	0
CONT_ASSIGN	822	1	1	100.00
CONT_ASSIGN	823	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
204	1	1
228	1	1
229	1	1
231	1	1
232	1	1
264	2	2
268	1	1
283	1	1
338	1	1
340	1	1
358	1	1
369	1	1
370	1	1
371	1	1
418	1	1
419	1	1
420	1	1
442	1	1
447	1	1
448	1	1
449	1	1
458	1	1
460	1	1
471	1	1
473	1	1
481	1	1
482	1	1
484	1	1
490	1	1
494	1	1
495	1	1
503	1	1
504	1	1
507	1	1
509	1	1
514	1	1
545	1	1
546	1	1
547	1	1
548	1	1
549	1	1
550	1	1
551	1	1
552	1	1
553	1	1
558	1	1
559	1	1
560	1	1
561	1	1
564	1	1
568	1	1
569	1	1
571	1	1
582	1	1
587	1	1
588	1	1
707	1	1
708	1	1
709	1	1
711	1	1
712	1	1
713	1	1
714	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
748	1	1
750	1	1
753	1	1
754	1	1
758	1	1
759	1	1
760	1	1
762	1	1
763	1	1
768	1	1
785	1	1
816		unreachable
822	1	1
823	1	1

---

Cond Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Conditions	179	143	79.89
Logical	179	143	79.89
Non-Logical	0	0
Event	0	0

 LINE       204
 EXPRESSION (ctrl_lfsr_en | data_lfsr_en | sideload_lfsr_en)
             ------1-----   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       273
 EXPRESSION (otp_key_i.creator_root_key_share0_valid & otp_key_i.creator_root_key_share1_valid)
             -------------------1-------------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (op_start & op_done)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       369
 EXPRESSION (reg2hw.sw_binding_regwen.qe & ((~reg2hw.sw_binding_regwen.q)))
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       370
 EXPRESSION (reg2hw.slot_policy_regwen.qe & ((~reg2hw.slot_policy_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       371
 EXPRESSION (reg2hw.max_key_ver_regwen.qe & ((~reg2hw.max_key_ver_regwen.q)))
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       418
 EXPRESSION (sw_binding_regwen & cfg_regwen)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       419
 EXPRESSION (slot_policy_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (max_key_ver_regwen & cfg_regwen)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (creator_seed_vld & devid_vld & health_state_vld & rom_digest_vld)
             --------1-------   ----2----   --------3-------   -------4------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       504
 EXPRESSION ((dest_sel == Aes) ? aes_seed : ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed)))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       504
 SUB-EXPRESSION (dest_sel == Aes)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       504
 SUB-EXPRESSION ((dest_sel == Kmac) ? kmac_seed : ((dest_sel == Otbn) ? otbn_seed : none_seed))
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       504
 SUB-EXPRESSION (dest_sel == Kmac)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       504
 SUB-EXPRESSION ((dest_sel == Otbn) ? otbn_seed : none_seed)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       504
 SUB-EXPRESSION (dest_sel == Otbn)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       509
 EXPRESSION (active_key_slot.valid ? ({reg2hw.key_version, reg2hw.salt, dest_seed, output_key}) : ({GenLfsrCopies {lfsr[31:0]}}))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       558
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       558
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       559
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       559
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       560
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       561
 EXPRESSION (adv_en & (active_key_slot.boot_stage == Creator))
             ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       561
 SUB-EXPRESSION (active_key_slot.boot_stage == Creator)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       564
 EXPRESSION (adv_en & (active_key_slot.boot_stage == OwnerInt))
             ---1--   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       564
 SUB-EXPRESSION (active_key_slot.boot_stage == OwnerInt)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       569
 EXPRESSION (adv_en | gen_en)
             ---1--   ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       582
 EXPRESSION (((~key_vld)) | invalid_advance | ((~adv_dvalid[active_key_slot.boot_stage])))
             ------1-----   -------2-------   ---------------------3---------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Not Covered
0	1	0	Covered	T2,T3,T4
1	0	0	Not Covered

 LINE       587
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       588
 EXPRESSION (((~key_vld)) | ((~key_version_vld)))
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       660
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[0] : kmac_data[0][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       660
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(0 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(1 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(2 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(3 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(4 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(5 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(6 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       667
 EXPRESSION ((((~data_sw_en)) | wipe_key) ? data_rand[1] : kmac_data[1][(7 * 32)+:32])
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       667
 SUB-EXPRESSION (((~data_sw_en)) | wipe_key)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       750
 EXPRESSION (fault_errs ? 1'b1 : (fault_err_ack ? 1'b0 : fault_err_req_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       750
 SUB-EXPRESSION (fault_err_ack ? 1'b0 : fault_err_req_q)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       754
 EXPRESSION (op_errs ? 1'b1 : (op_err_ack ? 1'b0 : op_err_req_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       754
 SUB-EXPRESSION (op_err_ack ? 1'b0 : op_err_req_q)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       768
 EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T16

 LINE       785
 EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
             -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T16

---

Toggle Coverage for Module : keymgr_dpe

	Total	Covered	Percent
Totals	69	51	73.91
Total Bits	10582	5702	53.88
Total Bits 0->1	5291	2852	53.90
Total Bits 1->0	5291	2850	53.87

Ports	69	51	73.91
Port Bits	10582	5702	53.88
Port Bits 0->1	5291	2852	53.90
Port Bits 1->0	5291	2850	53.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T5,T6,T7	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T10	Yes	T3,T4,T10	INPUT
tl_i.a_user.rsvd[9:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
aes_key_o.key[0][1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][2]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][3]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][4]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][6:5]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][7]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][9:8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][10]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][13:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][14]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][15]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][17]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][21:20]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][22]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][23]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][25:24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][27:26]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][28]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][30:29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][34:32]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][35]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][36]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][38]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][41:39]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][45:42]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][46]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][47]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][49:48]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][51:50]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][52]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][53]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][54]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][64:56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][65]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][66]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][67]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][70:68]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][71]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[0][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][76:73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][77]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[0][78]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][80:79]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][81]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][83]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][86:84]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][90:88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][91]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][92]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][93]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][95:94]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][96]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][99:97]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][100]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][101]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][107:102]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][108]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][109]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][110]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][111]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][112]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][115:113]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][116]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][121:117]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][123:122]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][124]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][127:125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][128]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][129]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][132:130]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][143:134]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][144]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][147:145]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][148]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][153:149]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][154]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][157:155]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][158]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][161:160]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][163:162]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][166:164]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][167]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][169:168]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][170]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[0][172:171]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][173]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][181:174]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][183:182]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][188:184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][189]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][190]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][195:192]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][196]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][198:197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][199]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][207:200]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][208]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
aes_key_o.key[0][209]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][211]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][212]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[0][215:213]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][217]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][219:218]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][220]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][227:221]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][228]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[0][229]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][230]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][231]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][234]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][235]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][237:236]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][238]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][239]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
aes_key_o.key[0][240]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][242:241]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][246:243]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][247]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][248]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][249]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][254:250]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[0][255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][8]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][10:9]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][16:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][17]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][25:20]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][26]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][27]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][28]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][31:29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][32]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][33]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][34]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][35]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][36]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][38]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][39]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][40]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][43:41]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][44]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][45]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][46]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][47]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][48]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][49]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][50]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][51]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][52]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][54:53]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][57]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
aes_key_o.key[1][58]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][62:59]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][65:63]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][67:66]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][68]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][69]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
aes_key_o.key[1][70]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][71]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][77:74]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][78]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][84:79]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][86:85]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][88:87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][89]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][90]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
aes_key_o.key[1][95:91]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][96]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][104:97]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][105]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][106]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[1][108:107]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][111:109]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][112]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][114:113]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][115]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][116]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][117]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][119:118]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][120]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][124:121]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][126]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][127]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][131:128]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][132]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][138:133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][140:139]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][142:141]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][143]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][148:144]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][149]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[1][151:150]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][152]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][155:153]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][156]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][158:157]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][159]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][174:160]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][175]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][176]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][177]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][178]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][179]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][184:180]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][186:185]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][189:187]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][190]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][191]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][193:192]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][194]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][196:195]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][203:198]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][204]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][206:205]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][207]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[1][208]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][209]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][212:211]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][213]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][214]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][215]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][220:217]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][221]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
aes_key_o.key[1][228:222]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][229]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][231:230]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][232]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][235:233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][236]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
aes_key_o.key[1][237]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][238]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][251:239]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][253:252]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.key[1][255:254]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
aes_key_o.valid	No	No		Yes	T2,T3,T4	OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
kmac_key_o.valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][9:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][10]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][13:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][14]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][16:15]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][17]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][18]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][20]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][21]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][23:22]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][24]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][25]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][26]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][27]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][28]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
otbn_key_o.key[0][30:29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][31]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][34:32]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][35]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][36]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][38]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][41:39]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][42]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][43]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][44]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][45]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][46]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][50:47]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][51]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][52]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][53]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][54]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][55]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][60:56]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][61]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][63:62]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][64]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][70:65]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][71]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][76:74]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][78:77]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][79]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][81:80]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][83:82]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][84]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][85]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][86]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][88:87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][89]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][90]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][92:91]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][93]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][95:94]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][96]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][105:97]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][106]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][115:107]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][116]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][122:117]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][123]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][124]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][127:126]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][128]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][129]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][130]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][135:131]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][136]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][140:137]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][141]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][146:142]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][147]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][150:148]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][151]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][152]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][154:153]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][155]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][163:156]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][164]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][165]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][168:166]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][170]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][171]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][179:172]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][181:180]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][183:182]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][186:185]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][187]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][189:188]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][191:190]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][192]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][193]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][194]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][195]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][196]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][197]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][199:198]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][200]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][201]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][203:202]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][204]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][211:205]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][213:212]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][215:214]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][219:217]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][221:220]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][222]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][223]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][227:224]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][228]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][232:229]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][233]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][236:234]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][238:237]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][240:239]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][241]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][252:242]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][253]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][254]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][259:255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][260]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][261]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][262]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][263]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][266:264]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][267]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][268]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][270:269]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][271]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][275:272]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][276]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
otbn_key_o.key[0][277]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][280:278]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][281]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][287:282]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][288]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][290:289]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][291]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][293:292]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][294]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][301:295]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][302]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][308:303]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][309]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][315:310]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][316]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][320:317]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][321]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][322]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][323]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][324]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][325]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][326]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][327]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][330:328]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][331]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][333:332]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][334]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][335]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][337:336]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][341:338]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][343:342]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][344]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][345]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][346]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][349:347]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][350]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][351]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][352]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][353]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][359:354]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][360]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][361]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][362]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][375:363]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][376]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][377]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][378]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[0][383:379]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][2:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][3]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][9:4]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][10]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][12:11]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][14:13]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][15]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][18:16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][19]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][26:20]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][27]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][28]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][33:29]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][34]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][35]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
otbn_key_o.key[1][36]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][37]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][51:38]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][52]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][57:53]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][58]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][60:59]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][61]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][66:62]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][67]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][68]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][69]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][70]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][71]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][72]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][73]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][76:74]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][77]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][86:78]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][87]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][98:88]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][99]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][115:100]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][116]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][119:117]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][120]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][121]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][122]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][124:123]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][125]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][129:126]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][130]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][132:131]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][133]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][136:134]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][137]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][143:138]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][144]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][149:145]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][150]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][153:151]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][154]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][159:155]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][160]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][161]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][167:162]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][168]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][171:169]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][172]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][173]	Yes	Yes	T3,T4,T8	Yes	T3,T4,T8	OUTPUT
otbn_key_o.key[1][175:174]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][177:176]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][178]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][183:179]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][185:184]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][193:186]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][194]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][204:195]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][205]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][206]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][208:207]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][209]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][214:210]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][215]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][216]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][217]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][218]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][220:219]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][221]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][226:222]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][227]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][229:228]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][230]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][237:231]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][238]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][239]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][240]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][244:241]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][245]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][246]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][249:247]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][250]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][252:251]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][253]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][254]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][256:255]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][257]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][266:258]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][267]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][268]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][269]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][274:270]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][275]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][280:276]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][281]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][288:282]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][289]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][290]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][291]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][292]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][293]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][304:294]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][305]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][307:306]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][309:308]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][310]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][311]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][312]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][314:313]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][315]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][316]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][317]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][319:318]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][320]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][321]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][331:322]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][332]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][335:333]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][337:336]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][342:338]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][343]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][344]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][347:345]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][348]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][349]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][354:350]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][355]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][357:356]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][358]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][359]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][364:360]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][365]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][366]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][368:367]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][372:369]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][373]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][376:374]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][377]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][379:378]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][380]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.key[1][383:381]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otbn_key_o.valid	No	No		Yes	T2,T3,T4	OUTPUT
kmac_data_o.last	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
kmac_data_o.strb[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
kmac_data_o.valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
kmac_data_i.done	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T5,T6,T7	Yes	T2,T3,T4	INPUT
lc_keymgr_div_i[127:0]	No	No		No		INPUT
otp_key_i.owner_seed_valid	No	No		No		INPUT
otp_key_i.owner_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_seed_valid	No	No		No		INPUT
otp_key_i.creator_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	No	No		No		INPUT
otp_device_id_i[255:0]	No	No		No		INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i.edn_fips	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i.edn_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
rom_digest_i[0].valid	No	No		No		INPUT
rom_digest_i[0].data[255:0]	No	No		No		INPUT
rom_digest_i[1].valid	No	No		No		INPUT
rom_digest_i[1].data[255:0]	No	No		No		INPUT
intr_op_done_o	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T15,T16	Yes	T1,T15,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T15,T16	Yes	T1,T15,T16	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : keymgr_dpe

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	504	4	4	100.00
TERNARY	509	2	2	100.00
TERNARY	750	3	2	66.67
TERNARY	754	3	3	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
TERNARY	660	2	2	100.00
TERNARY	667	2	2	100.00
IF	758	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	504	((dest_sel == Aes)) ? 
-2-:	504	((dest_sel == Kmac)) ? 
-3-:	504	((dest_sel == Otbn)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T4
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(active_key_slot.valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	(fault_errs) ? 
-2-:	750	(fault_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	754	(op_errs) ? 
-2-:	754	(op_err_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	660	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	667	(((~data_sw_en) | wipe_key)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	758	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	25	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	25	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvDataWidth_A	104	104	0	0
AesKeyKnownO_A	6070095	6014993	0	0
AlertKnownO_A	6070095	6014993	0	0
ErrCntMatch_A	104	104	0	0
FaultCntMatch_A	104	104	0	0
FpvSecCmCtrlCntAlertCheck_A	6070095	70	0	0
FpvSecCmCtrlDataFsmCheck_A	6070095	70	0	0
FpvSecCmCtrlMainFsmCheck_A	6070095	70	0	0
FpvSecCmCtrlOpFsmCheck_A	6070095	70	0	0
FpvSecCmKmacIfCntAlertCheck_A	6070095	70	0	0
FpvSecCmKmacIfFsmCheck_A	6070095	70	0	0
FpvSecCmRegWeOnehotCheck_A	6070095	70	0	0
FpvSecCmReseedCtrlCntAlertCheck_A	6070095	70	0	0
FpvSecCmSideloadCtrlFsmCheck_A	6070095	70	0	0
GenDataWidth_A	104	104	0	0
IntrKnownO_A	6070095	6014993	0	0
KeyWidthEqualityCheck_A	104	104	0	0
KmacDataKnownO_A	6040356	5985254	0	0
KmacKeyKnownO_A	6070095	6014993	0	0
KmacMaskCheck_A	104	104	0	0
LfsrWidth_A	104	104	0	0
OtbnKeyKnownO_A	6070095	6014993	0	0
OutputKeyDiff_A	104	104	0	0
TlAReadyKnownO_A	6070095	6014993	0	0
TlDValidKnownO_A	6070095	6014993	0	0

AdvDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

AesKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

ErrCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

FaultCntMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

FpvSecCmCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmCtrlDataFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmCtrlMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmCtrlOpFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmKmacIfCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmKmacIfFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmReseedCtrlCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

FpvSecCmSideloadCtrlFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	70	0	0
T5	39833	10	0	0
T6	27237	10	0	0
T7	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	57368	0	0	0
T24	1227	0	0	0
T25	1352	0	0	0
T26	166198	0	0	0
T27	1080	0	0	0
T28	1159	0	0	0
T29	860	0	0	0
T30	61702	0	0	0

GenDataWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

KeyWidthEqualityCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

KmacDataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6040356	5985254	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

KmacKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

KmacMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

LfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OtbnKeyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

OutputKeyDiff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104	104	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6070095	6014993	0	0
T1	1232	1158	0	0
T2	95113	95045	0	0
T3	73532	73470	0	0
T4	13491	13416	0	0
T8	45632	45547	0	0
T9	260855	260804	0	0
T10	34776	34712	0	0
T15	739	641	0	0
T16	1736	1645	0	0
T17	932	840	0	0