Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	7368633	9752	0	0
intr_enable_rd_A	7368633	2219	0	0
key_version_rd_A	7368633	2032	0	0
reseed_interval_regwen_rd_A	7368633	812	0	0
salt_0_rd_A	7368633	2337	0	0
salt_1_rd_A	7368633	2148	0	0
salt_2_rd_A	7368633	2059	0	0
salt_3_rd_A	7368633	2309	0	0
salt_4_rd_A	7368633	2194	0	0
salt_5_rd_A	7368633	2037	0	0
salt_6_rd_A	7368633	2125	0	0
salt_7_rd_A	7368633	2059	0	0
sideload_clear_rd_A	7368633	1945	0	0
slot_policy_rd_A	7368633	2752	0	0
sw_binding_0_rd_A	7368633	2157	0	0
sw_binding_1_rd_A	7368633	2168	0	0
sw_binding_2_rd_A	7368633	2222	0	0
sw_binding_3_rd_A	7368633	2061	0	0
sw_binding_4_rd_A	7368633	2102	0	0
sw_binding_5_rd_A	7368633	2110	0	0
sw_binding_6_rd_A	7368633	2157	0	0
sw_binding_7_rd_A	7368633	2068	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	9752	0	0
T18	2627	22	0	0
T19	13484	686	0	0
T20	10836	1	0	0
T32	2491	268	0	0
T33	2646	355	0	0
T34	4717	2	0	0
T35	4617	1	0	0
T52	0	2	0	0
T60	0	5	0	0
T65	3178	37	0	0
T69	1637	0	0	0
T70	1091	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2219	0	0
T19	13484	17	0	0
T20	10836	38	0	0
T35	4617	0	0	0
T39	0	4	0	0
T52	0	39	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	6	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	6	0	0
T87	0	13	0	0
T88	0	6	0	0
T90	0	15	0	0
T92	0	28	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2032	0	0
T19	13484	4	0	0
T20	10836	38	0	0
T35	4617	0	0	0
T39	0	2	0	0
T46	0	34	0	0
T52	0	39	0	0
T56	0	75	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	4	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	3	0	0
T87	0	8	0	0
T101	0	1	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	812	0	0
T19	13484	11	0	0
T39	14738	9	0	0
T46	20342	0	0	0
T50	16637	0	0	0
T55	0	8	0	0
T92	1239	0	0	0
T94	4782	21	0	0
T95	1620	0	0	0
T96	1804	0	0	0
T102	0	71	0	0
T103	0	18	0	0
T104	0	3	0	0
T105	0	42	0	0
T106	0	8	0	0
T107	0	19	0	0
T108	1580	0	0	0
T109	1444	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2337	0	0
T19	13484	10	0	0
T20	10836	22	0	0
T35	4617	0	0	0
T39	0	9	0	0
T46	0	70	0	0
T52	0	48	0	0
T56	0	72	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	1	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	2	0	0
T87	0	11	0	0
T101	0	8	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2148	0	0
T19	13484	9	0	0
T20	10836	42	0	0
T35	4617	0	0	0
T39	0	15	0	0
T46	0	42	0	0
T52	10878	55	0	0
T56	0	87	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	4	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T87	0	3	0	0
T94	0	12	0	0
T101	0	9	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2059	0	0
T19	13484	10	0	0
T20	10836	49	0	0
T35	4617	0	0	0
T39	0	3	0	0
T46	0	46	0	0
T52	0	35	0	0
T56	0	74	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	5	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	4	0	0
T87	0	4	0	0
T101	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2309	0	0
T19	13484	17	0	0
T20	10836	50	0	0
T35	4617	0	0	0
T39	0	8	0	0
T46	0	34	0	0
T52	0	25	0	0
T56	0	79	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	4	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	3	0	0
T87	0	16	0	0
T101	0	8	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2194	0	0
T19	13484	25	0	0
T20	10836	29	0	0
T35	4617	0	0	0
T39	0	13	0	0
T46	0	46	0	0
T52	0	48	0	0
T56	0	77	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	2	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	4	0	0
T87	0	10	0	0
T101	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2037	0	0
T19	13484	1	0	0
T20	10836	38	0	0
T35	4617	0	0	0
T39	0	11	0	0
T46	0	56	0	0
T52	0	47	0	0
T56	0	88	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	2	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	2	0	0
T87	0	5	0	0
T101	0	8	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2125	0	0
T19	13484	1	0	0
T20	10836	50	0	0
T35	4617	0	0	0
T39	0	6	0	0
T46	0	58	0	0
T52	0	47	0	0
T56	0	104	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	5	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	1	0	0
T87	0	12	0	0
T101	0	2	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2059	0	0
T19	13484	5	0	0
T20	10836	33	0	0
T35	4617	0	0	0
T39	0	38	0	0
T46	0	37	0	0
T52	0	28	0	0
T56	0	87	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	3	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	9	0	0
T87	0	9	0	0
T101	0	9	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	1945	0	0
T19	13484	13	0	0
T20	10836	43	0	0
T35	4617	0	0	0
T39	0	4	0	0
T46	0	32	0	0
T52	0	41	0	0
T56	0	57	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	9	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	1	0	0
T87	0	1	0	0
T101	0	5	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2752	0	0
T19	13484	23	0	0
T20	10836	76	0	0
T35	4617	0	0	0
T39	0	9	0	0
T46	0	117	0	0
T52	0	86	0	0
T56	0	142	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	6	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	3	0	0
T87	0	17	0	0
T101	0	7	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2157	0	0
T19	13484	36	0	0
T20	10836	44	0	0
T35	4617	0	0	0
T39	0	13	0	0
T46	0	33	0	0
T52	0	23	0	0
T56	0	82	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	1	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	7	0	0
T87	0	7	0	0
T101	0	2	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2168	0	0
T19	13484	17	0	0
T20	10836	54	0	0
T35	4617	0	0	0
T39	0	7	0	0
T46	0	78	0	0
T52	0	37	0	0
T56	0	62	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	1	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	7	0	0
T87	0	9	0	0
T101	0	7	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2222	0	0
T19	13484	33	0	0
T20	10836	42	0	0
T39	14738	5	0	0
T46	0	18	0	0
T52	10878	47	0	0
T56	0	89	0	0
T67	5022	0	0	0
T87	2270	11	0	0
T88	1023	0	0	0
T89	2588	0	0	0
T90	995	0	0	0
T91	6897	0	0	0
T94	0	32	0	0
T101	0	8	0	0
T109	0	3	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2061	0	0
T19	13484	14	0	0
T20	10836	38	0	0
T35	4617	0	0	0
T39	0	12	0	0
T46	0	52	0	0
T52	0	38	0	0
T56	0	73	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	1	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	8	0	0
T87	0	2	0	0
T101	0	7	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2102	0	0
T19	13484	21	0	0
T20	10836	57	0	0
T35	4617	0	0	0
T39	0	4	0	0
T46	0	52	0	0
T52	0	45	0	0
T56	0	85	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	5	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	7	0	0
T87	0	7	0	0
T94	0	14	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2110	0	0
T19	13484	4	0	0
T20	10836	62	0	0
T35	4617	0	0	0
T39	0	13	0	0
T46	0	43	0	0
T52	0	31	0	0
T56	0	75	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	9	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	4	0	0
T87	0	4	0	0
T101	0	4	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2157	0	0
T19	13484	18	0	0
T20	10836	28	0	0
T35	4617	0	0	0
T39	0	14	0	0
T46	0	54	0	0
T52	0	37	0	0
T56	0	85	0	0
T60	7855	0	0	0
T66	7079	0	0	0
T69	1637	6	0	0
T70	1091	0	0	0
T71	10894	0	0	0
T72	16716	0	0	0
T86	1500	9	0	0
T87	0	6	0	0
T101	0	1	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7368633	2068	0	0
T19	13484	8	0	0
T20	10836	47	0	0
T39	0	6	0	0
T46	0	46	0	0
T52	10878	52	0	0
T56	0	67	0	0
T67	5022	0	0	0
T86	1500	1	0	0
T87	2270	8	0	0
T88	1023	0	0	0
T89	2588	0	0	0
T90	995	0	0	0
T91	6897	0	0	0
T94	0	13	0	0
T101	0	7	0	0