Unified Coverage Report :: Module :: keymgr_dpe_ctrl

Module : keymgr_dpe_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.88	94.29	87.24		61.54	90.62	85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl	83.88	94.29	87.24		61.54	90.62	85.71

---

Module Instance : tb.dut.u_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.88	94.29	87.24		61.54	90.62	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.37	95.49	82.38	100.00	76.67	89.38	92.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_data_en	80.02	92.31	50.00		77.78	80.00	100.00
u_err	79.62	96.08	62.79			80.00
u_hw_sel	100.00	100.00				100.00	100.00
u_op_state	93.33	100.00	66.67		100.00	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
TOTAL		140	132	94.29
ALWAYS	94	4	4	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
ALWAYS	224	3	3	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	238	3	3	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	264	3	3	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	289	22	22	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
ALWAYS	406	3	3	100.00
ALWAYS	413	54	46	85.19
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
ALWAYS	587	5	5	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	778	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
98	1	1
100	1	1
104	1	1
124	1	1
133	1	1
134	1	1
135	1	1
150	1	1
151	1	1
152	1	1
153	1	1
167	1	1
172	1	1
178	1	1
180	1	1
195	1	1
203	1	1
219	1	1
224	1	1
225	1	1
227	1	1
231	1	1
238	1	1
239	1	1
241	1	1
248	1	1
253	1	1
256	2	2
264	1	1
266	1	1
268	1	1
274	1	1
275	1	1
276	1	1
278	1	1
279	1	1
282	1	1
289	1	1
291	1	1
297	1	1
298	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
335	1	1
336	1	1
338	1	1
348	1	1
350	1	1
351	1	1
352	1	1
389	1	1
403	1	1
406	3	3
413	1	1
420	1	1
423	1	1
424	1	1
427	1	1
430	1	1
433	1	1
436	1	1
439	1	1
443	1	1
445	1	1
450	1	1
453	1	1
454	1	1
455	1	1
456	1	1
457	1	1
			MISSING_ELSE
463	1	1
467	1	1
468	1	1
469	0	1
470	0	1
471	1	1
472	1	1
			MISSING_ELSE
481	1	1
485	1	1
486	1	1
487	0	1
488	0	1
489	1	1
490		unreachable
491		unreachable
			MISSING_ELSE
498	1	1
502	1	1
504	1	1
505	0	1
506	0	1
508	1	1
515	1	1
518	1	1
522	1	1
523	0	1
524	1	1
525	1	1
			MISSING_ELSE
535	1	1
538	1	1
540	1	1
542	1	1
543	1	1
547	1	1
548	1	1
549	1	1
558	1	1
560	1	1
561	0	1
			MISSING_ELSE
568	1	1
580	1	1
581	1	1
587	1	1
588	1	1
592	1	1
593	1	1
594	1	1
			MISSING_ELSE
645	1	1
650	1	1
653	1	1
657	1	1
664	1	1
668	1	1
671	1	1
673	1	1
679	1	1
684	1	1
778	3	3

---

Cond Coverage for Module : keymgr_dpe_ctrl

	Total	Covered	Percent
Conditions	196	171	87.24
Logical	196	171	87.24
Non-Logical	0	0
Event	0	0

 LINE       124
 EXPRESSION ((op_i == OpDpeGenSwOut) | (op_i == OpDpeGenHwOut))
             -----------1-----------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       124
 SUB-EXPRESSION (op_i == OpDpeGenSwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       124
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       133
 EXPRESSION (op_start_i & (op_i == OpDpeAdvance) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       133
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       134
 EXPRESSION (op_start_i & (op_i == OpDpeGenHwOut) & en_i)
             -----1----   -----------2-----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       134
 SUB-EXPRESSION (op_i == OpDpeGenHwOut)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       135
 EXPRESSION (op_start_i & (op_i == OpDpeDisable) & en_i)
             -----1----   -----------2----------   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       135
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       150
 EXPRESSION (op_req & (op_i == OpDpeAdvance))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       150
 SUB-EXPRESSION (op_i == OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (op_req & gen_key_op)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       152
 EXPRESSION (op_req & (op_i == OpDpeErase))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       152
 SUB-EXPRESSION (op_i == OpDpeErase)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (op_req & (op_i == OpDpeDisable))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       153
 SUB-EXPRESSION (op_i == OpDpeDisable)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       167
 EXPRESSION (adv_req & op_ack & ( ~ (op_err | op_fault_err) ))
             ---1---   ---2--   --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       167
 SUB-EXPRESSION (op_err | op_fault_err)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T5

 LINE       195
 EXPRESSION (wipe_req ? SlotWipeAll : ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       195
 SUB-EXPRESSION ((state_q == StCtrlDpeRandom) ? SlotDestRandomize : ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel))
                 --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (state_q == StCtrlDpeRandom)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION ((init_o & en_i & root_key_i.valid) ? SlotLoadRoot : op_update_sel)
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       195
 SUB-EXPRESSION (init_o & en_i & root_key_i.valid)
                 ---1--   --2-   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       203
 EXPRESSION 
 Number  Term
      1  (op_update & op_fault_err) ? SlotWipeAll : ((op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       203
 SUB-EXPRESSION (op_update & op_fault_err)
                 ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       203
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & dis_req) ? SlotWipeInternalOnly : ((op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION (op_update & dis_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION 
 Number  Term
      1  (op_update & (op_err | fsm_at_disabled)) ? SlotUpdateIdle : ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION (op_update & (op_err | fsm_at_disabled))
                 ----1----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION (op_err | fsm_at_disabled)
                 ---1--   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION ((op_update & adv_req) ? SlotLoadFromKmac : ((op_update & erase_req) ? SlotErase : SlotUpdateIdle))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION (op_update & adv_req)
                 ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION ((op_update & erase_req) ? SlotErase : SlotUpdateIdle)
                 -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       203
 SUB-EXPRESSION (op_update & erase_req)
                 ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       219
 EXPRESSION (prng_en_dis_inv_set ? 2'b11 : (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q))
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       219
 SUB-EXPRESSION (prng_reseed_done_i ? ({1'b0, prng_en_dis_inv_q[1]}) : prng_en_dis_inv_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       231
 EXPRESSION (random_req | wipe_req | prng_en_dis_inv_q[0])
             -----1----   ----2---   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	1	0	Covered	T6,T7,T8
1	0	0	Covered	T3,T4,T5

 LINE       248
 EXPRESSION (adv_req || gen_req)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       253
 EXPRESSION (active_key_slot_o.valid && ((!invalid_op)) && (adv_req || gen_req))
             -----------1-----------    -------2-------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       253
 SUB-EXPRESSION (adv_req || gen_req)
                 ---1---    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       256
 EXPRESSION (release_real_key ? active_key_slot_o.key[0] : ({EntropyRounds {entropy_i[0]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       256
 EXPRESSION (release_real_key ? active_key_slot_o.key[1] : ({EntropyRounds {entropy_i[1]}}))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       278
 EXPRESSION (op_ack & gen_key_op & ((~invalid_op)))
             ---1--   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       279
 EXPRESSION (update_sel == SlotWipeAll)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       364
 EXPRESSION (op_ack | random_ack)
             ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       364
 EXPRESSION (op_update | random_req)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       389
 EXPRESSION (op_req ? op_ack : (init_o | invalid_op))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       389
 SUB-EXPRESSION (init_o | invalid_op)
                 ---1--   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       450
 EXPRESSION (op_start_i & (((~en_i)) | (en_i & (op_i != OpDpeAdvance))))
             -----1----   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       450
 SUB-EXPRESSION (((~en_i)) | (en_i & (op_i != OpDpeAdvance)))
                 ----1----   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       450
 SUB-EXPRESSION (en_i & (op_i != OpDpeAdvance))
                 --1-   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       450
 SUB-EXPRESSION (op_i != OpDpeAdvance)
                -----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       489
 EXPRESSION (int'(cnt) == (EntropyRounds - 1))
            -----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Unreachable	T3,T4,T5

 LINE       504
 EXPRESSION (((!en_i)) | inv_state | ((~root_key_i.valid)))
             ----1----   ----2----   ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T5
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       518
 EXPRESSION (invalid_advance | invalid_erase | invalid_gen | (((~en_i)) & op_start_i))
             -------1-------   ------2------   -----3-----   ------------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Not Covered
0	0	1	0	Covered	T3,T4,T5
0	1	0	0	Not Covered
1	0	0	0	Covered	T3,T4,T5

 LINE       518
 SUB-EXPRESSION (((~en_i)) & op_start_i)
                 ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       522
 EXPRESSION (((!en_i)) | inv_state)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       580
 EXPRESSION (state_q == StCtrlDpeDisabled)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       581
 EXPRESSION (state_q == StCtrlDpeInvalid)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       592
 EXPRESSION (((|{error_o, fault_o})) ? OpDoneFail : OpDoneSuccess)
             -----------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       664
 EXPRESSION (active_slot_policy.retain_parent ? ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid) : (slot_src_sel_i != slot_dst_sel_i))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       664
 SUB-EXPRESSION ((slot_src_sel_i == slot_dst_sel_i) | destination_slot_valid)
                 -----------------1----------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Not Covered

 LINE       664
 SUB-EXPRESSION (slot_src_sel_i == slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       664
 SUB-EXPRESSION (slot_src_sel_i != slot_dst_sel_i)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       668
 EXPRESSION (adv_req & (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent))
             ---1---   --------------------------------------------2--------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       668
 SUB-EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
                 ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Not Covered

 LINE       671
 EXPRESSION (erase_req & ((~destination_slot_valid)))
             ----1----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Not Covered

 LINE       673
 EXPRESSION (gen_req & (((~active_key_slot_o.valid)) | ((~key_version_vld_o))))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       673
 SUB-EXPRESSION (((~active_key_slot_o.valid)) | ((~key_version_vld_o)))
                 --------------1-------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       679
 EXPRESSION (invalid_allow_child | invalid_max_boot_stage | invalid_src_slot | invalid_retain_parent)
             ---------1---------   -----------2----------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T3,T4,T5
0	0	0	1	Covered	T3,T4,T5
0	0	1	0	Not Covered
0	1	0	0	Covered	T3,T4,T5
1	0	0	0	Not Covered

 LINE       686
 EXPRESSION (state_intg_err_q | state_intg_err_d)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Not Covered

---

FSM Coverage for Module : keymgr_dpe_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	13	8	61.54
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlDpeAvailable	508	Covered	T3,T4,T5
StCtrlDpeDisabled	548	Covered	T3,T4,T5
StCtrlDpeDisabling	525	Covered	T3,T4,T5
StCtrlDpeEntropyReseed	457	Covered	T3,T4,T5
StCtrlDpeInvalid	454	Covered	T6,T7,T8
StCtrlDpeRandom	472	Covered	T3,T4,T5
StCtrlDpeReset	95	Covered	T1,T2,T3
StCtrlDpeRootKey	491	Covered	T3,T4,T5
StCtrlDpeWipe	523	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
StCtrlDpeAvailable->StCtrlDpeDisabling	525	Covered	T3,T4,T5
StCtrlDpeAvailable->StCtrlDpeWipe	523	Not Covered
StCtrlDpeDisabled->StCtrlDpeWipe	561	Not Covered
StCtrlDpeDisabling->StCtrlDpeDisabled	548	Covered	T3,T4,T5
StCtrlDpeEntropyReseed->StCtrlDpeInvalid	469	Not Covered
StCtrlDpeEntropyReseed->StCtrlDpeRandom	472	Covered	T3,T4,T5
StCtrlDpeRandom->StCtrlDpeInvalid	487	Not Covered
StCtrlDpeRandom->StCtrlDpeRootKey	491	Covered	T3,T4,T5
StCtrlDpeReset->StCtrlDpeEntropyReseed	457	Covered	T3,T4,T5
StCtrlDpeReset->StCtrlDpeInvalid	454	Covered	T6,T7,T8
StCtrlDpeRootKey->StCtrlDpeAvailable	508	Covered	T3,T4,T5
StCtrlDpeRootKey->StCtrlDpeInvalid	505	Not Covered
StCtrlDpeWipe->StCtrlDpeInvalid	542	Covered	T6,T7,T8

---

Branch Coverage for Module : keymgr_dpe_ctrl

	Line No.	Total	Covered	Percent
Branches		64	58	90.62
TERNARY	195	4	4	100.00
TERNARY	203	6	5	83.33
TERNARY	219	3	3	100.00
TERNARY	389	2	2	100.00
TERNARY	664	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	256	2	2	100.00
CASE	94	4	4	100.00
IF	224	2	2	100.00
IF	238	2	2	100.00
IF	264	2	2	100.00
CASE	291	6	6	100.00
IF	406	2	2	100.00
CASE	445	19	14	73.68
IF	588	4	4	100.00
IF	778	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv' or '../src/lowrisc_ip_keymgr_dpe_0.1/rtl/keymgr_dpe_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	195	(wipe_req) ? 
-2-:	195	((state_q == StCtrlDpeRandom)) ? 
-3-:	195	(((init_o & en_i) & root_key_i.valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	((op_update & op_fault_err)) ? 
-2-:	203	((op_update & dis_req)) ? 
-3-:	203	((op_update & (op_err | fsm_at_disabled))) ? 
-4-:	203	((op_update & adv_req)) ? 
-5-:	203	((op_update & erase_req)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Covered	T3,T4,T5
0	0	1	-	-	Covered	T3,T4,T5
0	0	0	1	-	Covered	T3,T4,T5
0	0	0	0	1	Covered	T3,T4,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	219	(prng_en_dis_inv_set) ? 
-2-:	219	(prng_reseed_done_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	(op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	(active_slot_policy.retain_parent) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(release_real_key) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	case (state_q)

Branches:

-1-	Status	Tests
StCtrlDpeReset StCtrlDpeEntropyReseed StCtrlDpeRandom StCtrlDpeRootKey	Covered	T1,T2,T3
StCtrlDpeAvailable	Covered	T3,T4,T5
StCtrlDpeWipe StCtrlDpeDisabling StCtrlDpeDisabled	Covered	T3,T4,T5
default	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	264	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	case (update_sel)

Branches:

-1-	Status	Tests
SlotDestRandomize	Covered	T3,T4,T5
SlotLoadRoot	Covered	T3,T4,T5
SlotLoadFromKmac	Covered	T3,T4,T5
SlotErase	Covered	T3,T4,T5
SlotWipeAll SlotWipeInternalOnly	Covered	T3,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	406	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	445	case (state_q)
-2-:	453	if (inv_state)
-3-:	456	if (advance_cmd)
-4-:	468	if ((!en_i))
-5-:	471	if (prng_reseed_ack_i)
-6-:	486	if ((!en_i))
-7-:	489	if ((int'(cnt) == (EntropyRounds - 1)))
-8-:	504	if ((((!en_i) | inv_state) | (~root_key_i.valid)))
-9-:	522	if (((!en_i) | inv_state))
-10-:	524	if (disable_cmd)
-11-:	560	if ((!en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StCtrlDpeReset	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StCtrlDpeReset	0	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeReset	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDpeEntropyReseed	-	-	1	-	-	-	-	-	-	-	Not Covered
StCtrlDpeEntropyReseed	-	-	0	1	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeEntropyReseed	-	-	0	0	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeRandom	-	-	-	-	1	-	-	-	-	-	Not Covered
StCtrlDpeRandom	-	-	-	-	0	1	-	-	-	-	Unreachable	T3,T4,T5
StCtrlDpeRandom	-	-	-	-	0	0	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeRootKey	-	-	-	-	-	-	1	-	-	-	Not Covered
StCtrlDpeRootKey	-	-	-	-	-	-	0	-	-	-	Covered	T3,T4,T5
StCtrlDpeAvailable	-	-	-	-	-	-	-	1	-	-	Not Covered
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
StCtrlDpeAvailable	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
StCtrlDpeWipe	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StCtrlDpeDisabling	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	1	Not Covered
StCtrlDpeDisabled	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
StCtrlDpeInvalid	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	588	if (op_done_o)
-2-:	592	((|{error_o, fault_o})) ? 
-3-:	593	if (op_start_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T4,T5
1	0	-	Covered	T3,T4,T5
0	-	1	Covered	T3,T4,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	778	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_dpe_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntZero_A	7723420	9336	0	0
DataEnDis_A	7670517	8986	0	0
DataEn_A	7670517	3929123	0	0
LoadKey_A	7701469	5665394	0	0
SameErrCnt_A	105	105	0	0
SecCmCFILinear_A	7754372	0	0	300
u_state_regs_A	7754372	7699609	0	0

CntZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7723420	9336	0	0
T3	52714	163	0	0
T4	43390	161	0	0
T5	54372	196	0	0
T6	0	120	0	0
T9	94405	177	0	0
T10	290051	159	0	0
T11	34271	186	0	0
T12	0	214	0	0
T13	0	161	0	0
T14	0	170	0	0
T16	636	0	0	0
T17	1063	0	0	0
T18	1161	0	0	0
T19	1529	0	0	0

DataEnDis_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7670517	8986	0	0
T3	52714	163	0	0
T4	43390	161	0	0
T5	54372	196	0	0
T6	0	20	0	0
T9	94405	177	0	0
T10	290051	159	0	0
T11	34271	186	0	0
T12	0	214	0	0
T13	0	161	0	0
T14	0	170	0	0
T16	636	0	0	0
T17	1063	0	0	0
T18	1161	0	0	0
T19	1529	0	0	0

DataEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7670517	3929123	0	0
T3	52714	1652	0	0
T4	43390	8029	0	0
T5	54372	10108	0	0
T9	94405	40748	0	0
T10	290051	172996	0	0
T11	34271	16790	0	0
T12	0	24765	0	0
T13	0	23695	0	0
T14	0	339129	0	0
T15	0	641758	0	0
T16	636	0	0	0
T17	1063	0	0	0
T18	1161	0	0	0
T19	1529	0	0	0

LoadKey_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7701469	5665394	0	0
T3	52714	2642	0	0
T4	43390	10681	0	0
T5	54372	13116	0	0
T9	94405	57371	0	0
T10	290051	257037	0	0
T11	34271	22421	0	0
T12	0	34078	0	0
T13	0	33947	0	0
T14	0	498162	0	0
T15	0	918929	0	0
T16	636	0	0	0
T17	1063	0	0	0
T18	1161	0	0	0
T19	1529	0	0	0

SameErrCnt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105	105	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7754372	0	0	300

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7754372	7699609	0	0
T1	1013	944	0	0
T2	855	796	0	0
T3	52714	52627	0	0
T4	43390	43305	0	0
T5	54372	54297	0	0
T9	94405	94309	0	0
T10	290051	289964	0	0
T16	636	571	0	0
T17	1063	999	0	0
T18	1161	1068	0	0