Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.11			92.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reseed_ctrl.u_reseed_cnt	81.08			81.08
tb.dut.u_kmac_if.u_cnt	95.24			95.24
tb.dut.u_ctrl.u_cnt	100.00			100.00

---

Module Instance : tb.dut.u_reseed_ctrl.u_reseed_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.78	100.00	93.33			100.00		u_reseed_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_kmac_if.u_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24			95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24			95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	100.00	76.06		100.00	89.74	100.00	u_kmac_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.u_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.88	94.29	87.24		61.54	90.62	85.71	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=31,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
95.24	95.24

tb.dut.u_kmac_if.u_cnt

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	42	40	95.24
Total Bits 0->1	21	20	95.24
Total Bits 1->0	21	20	95.24

Ports	9	8	88.89
Port Bits	42	40	95.24
Port Bits 0->1	21	20	95.24
Port Bits 1->0	21	20	95.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_cnt_i[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
set_cnt_i[1]	No	No		No		INPUT
set_cnt_i[4:2]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
81.08	81.08

tb.dut.u_reseed_ctrl.u_reseed_cnt

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	60	81.08
Total Bits 0->1	37	31	83.78
Total Bits 1->0	37	29	78.38

Ports	7	5	71.43
Port Bits	74	60	81.08
Port Bits 0->1	37	31	83.78
Port Bits 1->0	37	29	78.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[11:0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
cnt_o[12]	No	No		Yes	T33,T34,T35	OUTPUT
cnt_o[15:13]	No	No		No		OUTPUT
cnt_after_commit_o[11:0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[12]	No	No		Yes	T33,T34,T35	OUTPUT
cnt_after_commit_o[15:13]	No	No		No		OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_ctrl.u_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_reseed_ctrl.u_reseed_cnt

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	60	81.08
Total Bits 0->1	37	31	83.78
Total Bits 1->0	37	29	78.38

Ports	7	5	71.43
Port Bits	74	60	81.08
Port Bits 0->1	37	31	83.78
Port Bits 1->0	37	29	78.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[11:0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
cnt_o[12]	No	No		Yes	T33,T34,T35	OUTPUT
cnt_o[15:13]	No	No		No		OUTPUT
cnt_after_commit_o[11:0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[12]	No	No		Yes	T33,T34,T35	OUTPUT
cnt_after_commit_o[15:13]	No	No		No		OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_kmac_if.u_cnt

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	42	40	95.24
Total Bits 0->1	21	20	95.24
Total Bits 1->0	21	20	95.24

Ports	9	8	88.89
Port Bits	42	40	95.24
Port Bits 0->1	21	20	95.24
Port Bits 1->0	21	20	95.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_cnt_i[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
set_cnt_i[1]	No	No		No		INPUT
set_cnt_i[4:2]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.u_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	22	22	100.00
Total Bits 0->1	11	11	100.00
Total Bits 1->0	11	11	100.00

Ports	7	7	100.00
Port Bits	22	22	100.00
Port Bits 0->1	11	11	100.00
Port Bits 1->0	11	11	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T6,T7,T8	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
err_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT